Field-deployable hardware apparatus
In an aspect, a field-deployable hardware apparatus includes a stackable housing, a graphical processing unit disposed within the stackable housing, the graphical processing unit comprising a first plurality of processor cores, a general-purpose processor disposed within the stackable housing, the general-purpose processor comprising a second plurality of processor cores, at least a binary unit system disposed within the stackable housing and connecting the graphical processing unit to the general-purpose processor, and a memory communicatively connected to at least a core of the first plurality of cores and the second plurality of cores, the memory containing instructions configuring the at least a core to execute a hypervisor, wherein the hypervisor generates a virtual environment on the at least a core.
1. A field-deployable hardware apparatus comprising:
a stackable housing comprising one or more attachment features configured to secure the stackable housing to, and above or below, an adjacent housing of an adjacent field-deployable hardware apparatus, wherein the stackable housing comprises a waterproof construction including one or more sealable openings;
a graphical processing unit disposed within the stackable housing, the graphical processing unit comprising a first plurality of processor cores;
a general-purpose processor disposed within the stackable housing, the general-purpose processor comprising a second plurality of processor cores;
at least a binary unit system disposed within the stackable housing and connecting the graphical processing unit to the general-purpose processor; and
a memory communicatively connected to at least a core of the first plurality of cores and the second plurality of cores, the memory containing instructions configuring the at least a core to execute a hypervisor, wherein the hypervisor generates a virtual environment on the at least a core.
2. The apparatus of claim 1 , wherein the stackable housing comprises heat-dissipating construction.
3. The apparatus of claim 1 , wherein the general-purpose processor further comprises a reduced instruction set computer.
4. The apparatus of claim 1 , wherein the memory further comprises a per-processor memory.
5. The apparatus of claim 1 , wherein the memory comprises a boot partition.
6. The apparatus of claim 5 , wherein the boot partition comprises a trusted boot module.
7. The apparatus of claim 6 , wherein the trusted boot module is configured to perform a secure proof protocol.
8. The apparatus of claim 6 , wherein the trusted boot module is configured to perform an attested boot of the hypervisor.
9. The apparatus of claim 1 , wherein the hypervisor comprises a virtual machine monitor software.
10. The apparatus of claim 1 , wherein the hypervisor includes a bare metal hypervisor.
11. The apparatus of claim 1 , wherein the hypervisor includes a Type 2 hypervisor.
12. The apparatus of claim 1 , wherein the hypervisor is configured to execute at least a container.
13. The apparatus of claim 1 , wherein the hypervisor is configured to execute at least an operating system.
14. The apparatus of claim 1 , wherein the virtual environment comprises a virtual binary unit system.
15. The apparatus of claim 14 , wherein the virtual binary unit is communicatively connected to an exterior virtual environment.
16. The apparatus of claim 1 , wherein the hardware apparatus comprises a trusted platform module.
17. The apparatus of claim 1 further comprising a virtual-path cross-connect controller card.
18. The apparatus of claim 1 , wherein the memory contains instructions configuring the at least a core to verify a compliance of the hardware apparatus with at least a pre-determined safety standard from a trusted repository by monitoring an adherence of the hardware apparatus to the pre-defined operational rule.
19. The apparatus of claim 1 further comprising at least a high density input and output port communicatively connected to the graphical processing unit and the general-purpose processor.