IP Library Granted Patent US 12,591,539
Granted Patent B2
US 12,591,539 · App. 18/424,143 · Granted Mar 31, 2026

Rearranging data among processing elements of computational memory

Inventors: John Kitamura (Toronto, CA); Andrew Vincent Rock (Toronto, CA); William Martin Snelgrove (Toronto, CA)
Assignee: UNTETHER AI CORPORATION
G06F15/8023
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Quick Facts
Patent No.
US 12,591,539
App. No.
18/424,143
Granted
Mar 31, 2026
Kind
B2
Abstract

An array of interconnected processing elements is modelled as a graph of nodes. Each layer of the graph represents a possible arrangement of data elements within the array of interconnected processing elements. An edge between nodes of adjacent layers of the graph represents a movement of a data element between the nodes. Constraints are set for a starting arrangement of the data elements stored in the array, an ending arrangement of the data elements stored in the array, and a limit for each node of the graph to have one input edge from a previous layer and one output edge to a subsequent layer. The model and constraints are processed with an integer programming solver to obtain a program of movements of data elements among the interconnected processing elements. The program implements a rearrangement of the data elements from the starting arrangement to the ending arrangement.

Claims (46)

1 . A non-transitory machine-readable medium comprising instructions that, when executed by a processor, cause the processor to:

model an array of interconnected processing elements as a graph of nodes, wherein each layer of the graph represents a possible arrangement of data elements within the array of interconnected processing elements, and wherein an edge between nodes of adjacent layers of the graph represents a movement of a data element between the nodes;

set a first constraint as a starting arrangement of the data elements stored in the array of interconnected processing elements;

set a second constraint as an ending arrangement of the data elements stored in the array of interconnected processing elements;

set a third constraint to limit each node of the graph to have one input edge from a previous layer and one output edge to a subsequent layer;

select a number of layers for the graph based on a ratio of a greatest distance among the interconnected processing elements of the array to a maximum possible movement distance among PEs;

process the model, the first constraint, the second constraint, and the third constraint with an integer programming solver to obtain a program of movements of data elements among the interconnected processing elements, wherein the program implements a rearrangement of the data elements from the starting arrangement to the ending arrangement;

if the integer programming solver determines that the program is unattainable in the selected number of layers, then increase the number of layers for the graph and reperform the process with the integer programming solver; and

store the program for execution by a controller of the interconnected processing elements when the rearrangement is to be performed.

2 . The non-transitory machine-readable medium of claim 1 , wherein:

an edge of the graph includes a number of channels that corresponds to a number of nodes in a layer;

each channel is associated with a different interconnected processing element; and

a channel is activated for an edge of a node to indicate a starting interconnected processing element for the data element stored in the node.

3 . The non-transitory machine-readable medium of claim 1 , wherein the array of interconnected processing elements comprises a linear arrangement of processing elements.

4 . The non-transitory machine-readable medium of claim 1 , wherein the array of interconnected processing elements comprises a two-dimensional arrangement of processing elements.

5 . A computing system comprising:

one or more processors configured to collectively:

model an array of interconnected processing elements as a graph of nodes, wherein each layer of the graph represents a possible arrangement of data elements within the array of interconnected processing elements, and wherein an edge between nodes of adjacent layers of the graph represents a movement of a data element between the nodes;

set a first constraint as a starting arrangement of the data elements stored in the array of interconnected processing elements;

set a second constraint as an ending arrangement of the data elements stored in the array of interconnected processing elements;

set a third constraint to limit each node of the graph to have one input edge from a previous layer and one output edge to a subsequent layer;

select a number of layers for the graph based on a ratio of a greatest distance among the interconnected processing elements of the array to a maximum possible movement distance among PEs;

process the model, the first constraint, the second constraint, and the third constraint with an integer programming solver to obtain a program of movements of data elements among the interconnected processing elements, wherein the program implements a rearrangement of the data elements from the starting arrangement to the ending arrangement;

if the integer programming solver determines that the program is unattainable in the selected number of layers, then increase the number of layers for the graph and reperform the process with the integer programming solver; and

store the program for execution by a controller of the interconnected processing elements when the rearrangement is to be performed.

6 . The computing system of claim 5 , wherein:

an edge of the graph includes a number of channels that corresponds to a number of nodes in a layer;

each channel is associated with a different interconnected processing element; and

a channel is activated for an edge of a node to indicate a starting interconnected processing element for the data element stored in the node.

7 . The computing system of claim 5 , wherein the array of interconnected processing elements comprises a linear arrangement of processing elements.

8 . The computing system of claim 5 , wherein the array of interconnected processing elements comprises a two-dimensional arrangement of processing elements.

9 . A method comprising

modelling an array of interconnected processing elements as a graph of nodes, wherein each layer of the graph represents a possible arrangement of data elements within the array of interconnected processing elements, and wherein an edge between nodes of adjacent layers of the graph represents a movement of a data element between the nodes;

setting a first constraint as a starting arrangement of the data elements stored in the array of interconnected processing elements;

setting a second constraint as an ending arrangement of the data elements stored in the array of interconnected processing elements;

setting a third constraint to limit each node of the graph to have one input edge from a previous layer and one output edge to a subsequent layer;

selecting a number of layers for the graph based on a ratio of a greatest distance among the interconnected processing elements of the array to a maximum possible movement distance among PEs;

processing the model, the first constraint, the second constraint, and the third constraint with an integer programming solver to obtain a program of movements of data elements among the interconnected processing elements, wherein the program implements a rearrangement of the data elements from the starting arrangement to the ending arrangement;

if the integer programming solver determines that the program is unattainable in the selected number of layers, then increasing the number of layers for the graph and reperforming the processing with the integer programming solver; and

storing the program for execution by a controller of the interconnected processing elements when the rearrangement is to be performed.

10 . The method of claim 9 , wherein:

an edge of the graph includes a number of channels that corresponds to a number of nodes in a layer;

each channel is associated with a different interconnected processing element; and

a channel is activated for an edge of a node to indicate a starting interconnected processing element for the data element stored in the node.

11 . The method of claim 2 , wherein the array of interconnected processing elements comprises a linear arrangement of processing elements.

12 . The method of claim 2 , wherein the array of interconnected processing elements comprises a two-dimensional arrangement of processing elements.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2026
From: UNTETHER AI CORPORATION
To: AT-MEMORY COMPUTING LP
Reel/Frame 075495/0905 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2024
From: SNELGROVE, WILLIAM MARTIN; KITAMURA, JOHN; ROCK, ANDREW VINCENT
To: UNTETHER AI CORPORATION
Reel/Frame 066333/0905 →
Continuity (1)
Related Publication 20250245189A1 · Jul 31, 2025
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