Granted Patent B2

US 12,481,554 · App. 18/430,259 · Granted Nov 25, 2025

Inventor: Jawad Benhammadi (Pont de Claix, FR)

Assignee: STMicroelectronics International N.V.

G06F11/1068G06F11/1044

Abstract

Claims (22)

1 . A method of electrically-erasable programmable read-only memory (EEPROM) emulation in a phase-change memory of a circuit integrating a microprocessor, wherein the phase-change memory includes a data zone and an error correction zone, the method comprising the following steps:

defining a granularity for writing into lines of the data zone of the phase-change memory according to a size of each data packet to be written;

deactivating the error correction zone during EEPROM emulation;

associating with each data packet a first error correction code calculated by a program executed by said microprocessor; and

storing a plurality of data packets and their associated first error correction codes in a same line of the data zone of the phase-change memory.

2 . The method according to claim 1 , wherein each line of the phase-change memory in the data zone has a capacity of storing at least two data packets and their associated first error correction codes.

3 . The method according to claim 1 , wherein deactivating the error correction zone comprises deactivating calculation by a hardware operator of a second error correction code for the data zone of said same line.

4 . The method according to claim 1 , wherein each first error correction code is written after its associated data packet.

5 . The method according to claim 1 , wherein the plurality of data packets and their associated first error correction codes are written consecutively in said same line of the phase-change memory.

6 . The method according to claim 1 , wherein the granularity of writing depends on a parameter that can be modified by a user.

7 . An integrated circuit, comprising a phase-change memory and a microprocessor, configured to implement the method according to claim 1 .

8 . A method of electrically-erasable programmable read-only memory (EEPROM) emulation in a phase-change memory of a circuit integrating a microprocessor, wherein the phase-change memory includes a data zone and an error correction zone, the method comprising the following steps:

deactivating the error correction zone during EEPROM emulation;

associating a first data packet with a first error correction code calculated by a program executed by said microprocessor;

storing the first data packet and its associated first error correction code at a first location in a first line of the data zone of the phase-change memory;

associating a second data packet with a second error correction code calculated by the program executed by said microprocessor; and

storing the second data packet and its associated second error correction code at a second location in the first line of the data zone of the phase-change memory following the first location where the first data packet and its associated first error correction code are stored.

9 . The method according to claim 8 , further comprising:

associating a third data packet with a third error correction code calculated by the program executed by said microprocessor; and

storing the third data packet and its associated third error correction code at a third location in the first line of the data zone of the phase-change memory following the second location where the second data packet and its associated second error correction code are stored.

10 . The method according to claim 8 , wherein at least the first and second data packets and their associated first and second error correction codes are stored in said data zone of the line of the phase-change memory.

11 . An integrated circuit, comprising a phase-change memory and a microprocessor, configured to implement the method according to claim 8 .

Assignments (2)

Priority Claims (1)

Continuity (1)

References Cited (20)