Granted Patent B2

US 12,602,233 · App. 18/430,825 · Granted Apr 14, 2026

Inventor: Jawad Benhammadi (Pont de Claix, FR)

Assignee: STMicroelectronics International N.V.

G06F9/4403G06F21/78G06F9/4401G06F9/445G06F21/60

Abstract

Claims (20)

1 . A method for protecting N boot programs in a memory, N being an integer greater than 2, comprising:

increasing a size of a no-access region of the memory containing the N boot programs by an enlargement of the no-access region in response to execution of each boot program loaded into the memory, said enlargement having a value;

wherein the size of the no-access region of the memory is defined by a content of a first volatile storage register;

further comprising incrementing, in response to an end of execution of each boot program, a value of said content of the first volatile storage register by the value of the enlargement of the no-access region.

2 . The method according to claim 1 , further comprising:

loading each the N boot programs into successive zones of the memory; and

blocking access to each zone once a boot program stored in the zone has been executed;

wherein blocking comprises enlarging the size of the no-access region of the memory.

3 . The method according to claim 1 , further comprising loading each boot program, starting from a second one of the N boot programs, into the memory after a previous one of the N boot programs once access to a zone of the memory storing said previous one of the N boot programs has been closed by the enlargement of the no-access region.

4 . The method according to claim 1 , wherein incrementing the value comprises increasing the value of said content of the first volatile storage register by a number of memory sectors.

5 . The method according to claim 1 , wherein incrementing the value comprises monotonously increasing.

6 . The method according to claim 1 , wherein a content of a second volatile storage register comprises a value defining a status for access to the no-access region, wherein the status for access to the no-access region comprises an authorized status or a closed status.

7 . The method according to claim 6 , further comprising resetting the second volatile storage register only in response to a resetting of the memory.

8 . The method according to claim 6 , wherein the second volatile storage register stores the value defining the status for access to the no-access region over 1 bit.

9 . The method according to claim 6 , wherein the second volatile storage register stores the value defining the status for access to the no-access region over a plurality of bits.

10 . The method according to claim 9 , wherein an authorized status value and a closed status value defining the status for access to said no-access region are distant by more than one bit.

11 . The method according to claim 10 , further comprising, when the content of the second volatile storage register is different from either of said authorized status value and said closed status value, closing access to the no-access region until a resetting of the memory.

12 . The method according to claim 10 , further comprising, when the content of the second volatile storage register is different from either of said authorized status value and said closed status value, preventing modification of the content of the first volatile storage register.

13 . The method according to claim 1 , wherein a maximum size of the no-access region is predefined, and further comprising loading application programs outside of said maximum size of the no-access region.

14 . An electronic circuit configured to implement the method according to claim 1 .

Assignments (2)

Priority Claims (1)

Continuity (1)

References Cited (10)