Hysteretic control for load transient improvement in peak current control mode power converter architectures
In some embodiments, a system includes a power conversion system including at least one driver operatively coupled to at least one switch, a hysteretic control system, and driver control circuitry, operatively coupled to the at least one driver and the hysteretic control system, to receive at least one driver control signal from the hysteretic control system, and to control, based on the at least one driver control signal, operation of the at least one driver.
1 . A system comprising:
a power conversion system comprising:
a first driver and a second driver;
peak current mode control circuitry to generate a peak current mode control signal;
a hysteretic control system to generate at least one of a first driver control signal or a second driver control signal that is an inverse of the first driver control signal; and
driver control circuitry, having a first output operatively coupled to the first driver and a second output operatively coupled to the second driver, to receive at least one driver control signal from the hysteretic control system, and to control, based on at least one of the first driver control signal or the second driver control signal, operation of at least one of the first driver or the second driver;
wherein the hysteretic control system comprises a first hysteretic control subsystem, operatively coupled to a first input of the driver control circuitry, to generate the first driver control signal based on a hysteretic control signal; and
wherein the hysteretic control system further comprises a second hysteretic control subsystem operatively coupled to a second input of the driver control circuitry, the second hysteretic control subsystem being configured to generate the second driver control signal by performing a logical AND operation based on the hysteretic control signal and the peak current mode control.
2 . The system of claim 1 , wherein the hysteretic control system operates in response to a transient.
3 . The system of claim 1 , wherein the first input of the driver control circuitry is a set input of state storage circuitry comprising at least one of a flip-flop or a latch, and wherein the second input of the driver control circuitry is a reset input of the state storage circuitry.
4 . The system of claim 1 , wherein, to control the operation of at least one of the first driver or the second driver, the driver control circuitry is to:
enable the first driver in response to the first driver control signal being high; or
disable the first driver in response to the first driver control signal being low.
5 . The system of claim 1 , wherein the first hysteretic control subsystem comprises:
a comparator to generate a comparator output signal based on a feedback signal and a reference signal each received by the comparator;
an AND gate to generate an AND gate output signal based on the comparator output signal and a clock signal each received by the AND gate; and
an OR gate to generate the first driver control signal based on the hysteretic control signal and the AND gate output signal each received by the OR gate.
6 . The system of claim 5 , wherein the reference signal has a voltage that is less than a reference voltage for the power conversion system.
7 . The system of claim 6 , wherein the reference signal has a voltage that ranges between about 97% of the reference voltage and about 99% of the reference voltage.
8 . The system of claim 1 , wherein the peak current mode control circuitry comprises:
an error amplifier to generate an error amplifier signal based on a feedback signal and a reference signal each received by the error amplifier;
a compensation network to generate a compensated signal based on the error amplifier signal received by the compensation network;
a ramp voltage generator to generate a ramp voltage;
a combiner to generate a combined signal by combining the ramp voltage with a sensed current associated with a switch operatively coupled to the first driver; and
a comparator to generate the second driver control signal based on the combined signal and the compensated signal each received by the comparator.
9 . The system of claim 1 , wherein the power conversion system implements a direct current (DC) to DC (DC-to-DC) converter.
10 . A system comprising:
a power conversion system implementing a direct current (DC) to DC (DC-to-DC) converter operating in a peak current control mode, the power conversion system comprising:
a first driver operatively coupled to a first switch;
a second driver operatively coupled to a second switch;
a hysteretic control system, operating in response to a transient, the hysteretic control system comprising a first hysteretic control subsystem to generate a first driver control signal based on a hysteretic control signal, and a second hysteretic control subsystem to generate a second driver control signal that is an inverse of the first driver control signal;
driver control circuitry having a first input operatively coupled to the first hysteretic control subsystem, a second input operatively coupled to the second hysteretic control subsystem, a first output operatively coupled to the first driver and a second output operatively coupled to the second driver, the driver control circuitry to control, based on at least one of the first driver control signal or the second driver control signal, operation of at least one of the first driver or the second driver; and
peak current mode control circuitry operatively coupled to the second hysteretic control subsystem and configured to generate a peak current mode control signal, wherein the second hysteretic control subsystem is configured to generate the second driver control signal by performing a logical AND operation based on the hysteretic control signal and the peak current mode control signal.
11 . The system of claim 10 , wherein the first input of the driver control circuitry is a set input of state storage circuitry comprising at least one of a flip-flop or a latch, and wherein the second input of the driver control circuitry is a reset input of the state storage circuitry.
12 . The system of claim 10 , wherein, to control operation of at least one of the first driver or the second driver, the driver control circuitry is to:
enable the first driver in response to the first driver control signal being high; or
disable the first driver in response to the first driver control signal being low.
13 . The system of claim 10 , wherein the first hysteretic control subsystem comprises:
a comparator to generate a comparator output signal based on a feedback signal and a reference signal each received by the comparator, the reference signal having a voltage that is less than a reference voltage for the power conversion system;
an AND gate to generate an AND gate output signal based on the comparator output signal and a clock signal each received by the AND gate; and
an OR gate to generate the first driver control signal based on the hysteretic control signal and the AND gate output signal each received by the OR gate.
14 . The system of claim 10 , wherein the peak current mode control circuitry comprises:
an error amplifier to generate an error amplifier signal based on a feedback signal and a reference signal;
a compensation network to generate a compensated signal based on the error amplifier signal;
a ramp voltage generator to generate a ramp voltage;
a combiner to generate a combined signal by combining the ramp voltage with a sensed current associated with a switch operatively coupled to the first driver; and
a comparator to generate the second driver control signal based on the combined signal and the compensated signal.
15 . A method comprising:
receiving, by driver control circuitry of a power conversion system, at least one of a first driver control signal or a second driver control signal from a hysteretic control system of the power conversion system operatively coupled to a first driver and a second driver, wherein the second driver control signal is an inverse of the first driver control signal; and
controlling, by the driver control circuitry and based on at least one of the first driver control signal or the second driver control signal, operation of at least one of the first driver or the second driver
wherein the hysteretic control system comprises a first hysteretic control subsystem, operatively coupled to a first input of the driver control circuitry, to generate the first driver control signal based on a hysteretic control signal; and
wherein the hysteretic control system further comprises a second hysteretic control subsystem operatively coupled to a second input of the driver control circuitry, the second hysteretic control subsystem being configured to generate the second driver control signal by performing a logical AND operation based on the hysteretic control signal and a peak current mode control signal.
16 . The method of claim 15 , wherein the first input of the driver control circuitry is a set input of state storage circuitry comprising at least one of a flip-flop or a latch, and wherein the second input of the driver control circuitry is a reset input of the state storage circuitry.
17 . The method of claim 15 , wherein controlling the operation of at least one of the first driver or the second driver comprises:
enabling the first driver in response to the first driver control signal being high; or
disabling the first driver in response to the first driver control signal being low.
18 . The method of claim 15 , wherein the first hysteretic control subsystem comprises:
a comparator to generate a comparator output signal based on a feedback signal and a reference signal each received by the comparator;
an AND gate to generate an AND gate output signal based on the comparator output signal and a clock signal each received by the AND gate; and
an OR gate to generate the first driver control signal based on the hysteretic control signal and the AND gate output signal each received by the OR gate.
19 . The method of claim 18 , wherein the reference signal has a voltage that is less than a reference voltage for the power conversion system.
20 . The method of claim 19 , wherein the reference signal has a voltage that ranges between about 97% of the reference voltage and about 99% of the reference voltage.