Dynamic control of error management and signaling
Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds are configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device configures a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device tracks or counts errors in the data and determine whether the threshold has been satisfied. The memory device transmits (e.g., to the host device) an indication whether the threshold has been satisfied, and the system performs functions to correct the errors and/or prevent further errors. The memory device also identifies errors in received commands or identifies errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).
1. An apparatus comprising:
a memory array;
error correction code logic associated with the memory array and configured, based at least in part on a command, to generate a first error correction code for data, detect one or more errors in the data, and correct the one or more errors in the data; and
an error counter associated with the error correction code logic and configured to be incremented based at least in part on the error correction code logic detecting the one or more errors in the data.
2. The apparatus of claim 1 , wherein:
a first portion of the memory array is configured to store the data; and
the error correction code logic is configured to detect the one or more errors in the data using the first error correction code.
3. The apparatus of claim 1 , wherein the apparatus further comprises:
first logic associated with the error counter and configured to compare a value of the error counter to a threshold value.
4. The apparatus of claim 3 , wherein the first logic associated with the error counter is further configured to output an indication associated with the value of the error counter based at least in part on the value of the error counter satisfying the threshold value.
5. The apparatus of claim 3 , wherein the apparatus further comprises:
a controller configured to receive a second command to implement the error counter.
6. The apparatus of claim 3 , wherein the threshold value is based at least in part on an application associated with the data, a storage location for the data within the memory array, or both.
7. The apparatus of claim 3 , wherein the first logic is further configured to store the threshold value based at least in part on receiving an indication of the threshold value.
8. The apparatus of claim 3 , wherein the first logic is further configured to store a plurality of threshold values comprising at least the threshold value, each of the plurality of threshold values corresponding to a respective application associated with a respective set of data at the memory array.
9. An apparatus comprising:
an array of memory cells; and
a controller configured to cause the apparatus to:
identify a quantity of errors in data retrieved from the array of memory cells;
compare the quantity of errors to a first threshold quantity of errors; and
transmit a report indicating that the quantity of errors satisfies the first threshold quantity of errors.
10. The apparatus of claim 9 , wherein the controller is configured to cause the apparatus to:
receive a command that indicates to determine that the quantity of errors satisfies the first threshold quantity of errors.
11. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
retrieve the data from a bank of the array of memory cells.
12. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
increment an error counter for each error of the quantity of errors in the data; and
operate the apparatus in a mode in which the apparatus refrains from executing commands for the array of memory cells.
13. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
adjust a refresh rate for the array of memory cells based at least in part on detecting the quantity of errors.
14. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
identify a temperature of the array of memory cells; and
transmit an indication of the temperature of the array of memory cells.
15. The apparatus of claim 9 , wherein the controller is further configured to cause the apparatus to:
receive an indication of a second threshold quantity of errors for second data, wherein the second threshold quantity of errors is based at least in part on a second application associated with the second data.
16. The apparatus of claim 9 , wherein the first threshold quantity of errors comprises a threshold type of errors, a threshold of errors at a location of the array of memory cells, a threshold frequency of errors, or any combination thereof.
17. The apparatus of claim 9 , wherein the first threshold quantity of errors is based at least in part on a type of the data, a location of the data within the array of memory cells, or both.
18. An apparatus comprising:
an array of memory cells;
error correction code logic;
an error counter; and
a controller configured to cause the apparatus to:
receive a command associated with data at the array of memory cells;
generate, using the error correction code logic, a first error correction code for the data;
detect, using the error correction code logic, one or more errors in the data; and
incrementing the error counter based at least in part on detecting the one or more errors.
19. The apparatus of claim 18 , wherein the controller is configured to detect the one or more errors in the data using the first error correction code.
20. The apparatus of claim 18 , wherein the controller is further configured to:
compare a value of the error counter to a threshold value.