Method of monitoring a clock signal, corresponding device and system
A method comprises receiving an input clock signal having a clock frequency band between a lower frequency limit value and an upper frequency limit value, dividing the clock frequency band in a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value, comparing the frequency of the clock signal with the set of frequency limit values to produce comparison indicators having a first logic value when the measured frequency fails to exceed at least one frequency limit value and having a second logic value when the measured frequency exceeds the at least one frequency limit value, and, as a result of at least one of the logic values of comparison indicators having the second logic value, producing a global flag signal indicating that the measured frequency falls outside of a frequency range.
1 . A method, comprising:
receiving an input clock signal having a clock period and a clock frequency band between a lower frequency limit value and an upper frequency limit value;
receiving a reference clock signal having a reference clock period;
dividing the clock frequency band into a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value;
measuring a frequency of the input clock signal;
performing a set of comparisons of the measured frequency with the set of frequency limit values, producing, as a result, a set of comparison indicators comprising comparison indicators having a first logic value in response to the measured frequency failing to exceed at least one frequency limit value of the set of frequency limit values and having a second logic value in response to the measured frequency exceeding the at least one frequency limit value of the set of frequency limit values;
producing a global flag signal as a result of at least one of the logic values of comparison indicators in the set of comparison indicators having the second logic value; and
providing the global flag signal to user circuitry, the global flag signal indicating that the measured frequency falls outside of at least one of the frequency ranges.
2 . The method of claim 1 , comprising:
at lapse of multiples of a product of a first integer N times the reference clock period of the reference clock signal, storing in a set of flag registers the logic values of comparison indicators in the set of comparison indicators, and
at lapse of multiples of a product of a second integer P times the reference clock period of the reference clock signal, logically combining the logic values stored in the set of flag registers.
3 . The method of claim 1 , wherein performing the set of comparisons of the measured frequency comprises performing the set of comparisons of the measured frequency with each frequency in the set of frequency limit values, and the method further comprises:
pairwise, logically combining comparison indicators in the set of comparison indicators using a logic gate; and
storing the logic value of each of the pairwise logic combinations of comparison indicators in the set of comparison indicators in a respective flag register of a set of flag registers; and
producing the global flag signal as a result of at least one of the logic values stored in the flag registers having the second logic value.
4 . The method of claim 1 , wherein:
performing the set of comparisons of the measured frequency with the set of frequency limit values comprises:
ordering the set of frequency limit values in an increasing or decreasing order of limit values; and
performing a pair of comparisons of the measured frequency with a respective pair of sequentially adjacent frequency limit values in the ordered set of frequency limit values, producing as a result a pair of comparison indicators; and
the method further comprises:
logically combining the pair of comparison indicators using a logic gate;
storing the logic value of the logic combination of each pair of comparison indicators in a respective flag register of a set of flag registers; and
producing the global flag signal as a result of at least one of the logic values stored in the set of flag registers having the second logic value.
5 . The method of claim 1 , wherein:
performing the set of comparisons of the measured frequency with the set of frequency limit values comprises:
ordering the set of frequency limit values in increasing or decreasing order of values; and
alternating selecting the upper frequency limit value and the lower frequency limit value and alternating performing a comparison of the measured frequency with the upper frequency limit value and the lower frequency limit value, respectively; and
the method further comprises:
storing the logic values of the comparison indicators produced as a result of the alternated comparisons in a respective flag register,
logically combining the stored logic values using a logic gate; and
producing the global flag signal as a result of at least one of the logic values stored in the flag registers having the second logic value.
6 . A device, comprising:
an input clock node configured to receive an input clock signal having a clock period and a clock frequency band between a lower frequency limit value and an upper frequency limit value;
a reference clock node configured to receive a reference clock signal having a reference clock period;
a logic control unit configured to divide the clock frequency band in a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value;
a frequency counter circuit coupled to the input clock node to receive the input clock signal therefrom, the frequency counter circuit configured to measure a frequency of the input clock signal;
a set of comparators coupled to the frequency counter circuit to receive the measured frequency of the input clock signal therefrom, the set of comparators configured to perform a set of comparisons of the measured frequency with the set of frequency limit values, producing, as a result, a set of comparison indicators comprising comparison indicators having a first logic value in response to the measured frequency failing to exceed at least one frequency limit value of the set of frequency limit values and having a second logic value in response to the measured frequency exceeding the at least one frequency limit value of the set of frequency limit values; and
logic circuitry coupled to the set of comparators to receive the set of comparison indicators therefrom, the logic circuitry configured to produce a global flag signal as a result of at least one of the logic values of comparison indicators in the set of comparison indicators having the second logic value, the logic circuitry further configured to provide the global flag signal to user circuitry, the global flag signal indicating that the measured frequency falls outside of at least one of the frequency ranges.
7 . The device of claim 6 , further comprising:
a set of flag registers coupled to the set of comparators configured to store, at lapse of multiples of a product of a first integer N times the reference clock period of the reference clock signal, the logic values of the comparison indicators in the set of comparison indicators; and
at least one gate configured to logically combine, at lapse of multiples of a product of a second integer P times the reference clock period of the reference clock signal, the logic values stored in the set of flag registers.
8 . The device of claim 6 , wherein the set of comparators is configured to perform the set of comparisons of the measured frequency with each frequency in the set of frequency limit values, and wherein the device further comprises:
a set of logic gates coupled to the set of comparators to receive the set of comparison indicators therefrom, the set of logic gates configured to logically combine, pairwise, comparison indicators in the set of comparison indicators; and
a set of flag registers coupled to the set of logic gates, the set of flag registers configured to store the logic value of each of the pairwise logic combinations of comparison indicators in the set of comparison indicators in respective flag registers of the set of flag registers;
wherein the logic circuitry is configured to produce the global flag signal as a result of at least one of the logic values stored in the set of flag registers having the second logic value.
9 . The device of claim 6 , wherein:
the logic control unit is configured to order the set of frequency limit values in an increasing or decreasing order of limit values;
the set of comparators comprises a pair of comparators configured to perform comparisons of the measured frequency with a respective pair of sequentially adjacent frequency limit values in the ordered set of frequency limit values; and
the device further comprises:
a logic gate coupled to the pair of comparators to receive a pair of comparison indicators therefrom, the logic gate configured to logically combine the pair of comparison indicators;
a set of flag registers coupled to the logic gate, the set of flag registers configured to store the logic value of the logic combination of each pair of comparison indicators in a respective flag register of the set of flag registers; and
wherein the logic circuitry is configured to produce the global flag signal as a result of at least one of the logic values stored in the set of flag registers having the second logic value.
10 . The device of claim 6 , wherein:
the logic control unit is configured to order the set of frequency limit values in increasing or decreasing order of values, and alternately select the upper frequency limit value and the lower frequency limit value;
the set of comparators comprises a comparator that is configured to alternating performing a comparison of the measured frequency with the upper frequency limit value and the lower frequency limit value, respectively; and
the device further comprises a pair of flag registers coupled to the set of comparators and configured to store the logic values of the comparison indicators produced as a result of the alternated comparisons in respective flag registers;
wherein the logic circuitry comprises a logic gate coupled to the pair of flag registers and configured to logically combine the stored logic values.
11 . A system, comprising:
an antenna configured to receive a satellite positioning signal as an analog signal, processing circuitry coupled to the antenna and configured to apply analog-to-digital (ADC) processing to the received satellite positioning signal; and
at least one device coupled to the processing circuitry to provide thereto a global flag signal, wherein each device comprises:
an input clock node configured to receive an input clock signal having a clock period and a clock frequency band between a lower frequency limit value and an upper frequency limit value;
a reference clock node configured to receive a reference clock signal having a reference clock period;
a logic control unit configured to divide the clock frequency band into a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value;
a frequency counter circuit coupled to the input clock node to receive the input clock signal therefrom, the frequency counter circuit configured to measure a frequency of the input clock signal;
a set of comparators coupled to the frequency counter circuit to receive the measured frequency of the input clock signal therefrom, the set of comparators configured to perform a set of comparisons of the measured frequency with the set of frequency limit values, producing as a result a set of comparison indicators comprising comparison indicators having a first logic value in response to the measured frequency failing to exceed at least one frequency limit value of the set of frequency limit values and having a second logic value in response to the measured frequency exceeding the at least one frequency limit value of the set of frequency limit values; and
logic circuitry coupled to the set of comparators to receive the set of comparison indicators therefrom, the logic circuitry configured to produce the global flag signal as a result of at least one of the logic values of comparison indicators in the set of comparison indicators having the second logic value, the logic circuitry further configured to provide the global flag signal to user circuitry, the global flag signal indicating that the measured frequency falls outside of at least one of the frequency ranges.
12 . The system of claim 11 , wherein the system is equipped on-board a vehicle.
13 . The system of claim 12 , wherein the vehicle is a road vehicle.
14 . The system of claim 13 , wherein the vehicle is an autonomous road vehicle.
15 . The system of claim 11 , wherein the system is a Global Navigation Satellite System (GNSS) navigation system.
16 . The system of claim 11 , wherein the system comprises more than one device.
17 . The system of claim 11 , wherein each device further comprises:
a set of flag registers coupled to the set of comparators configured to store, at lapse of multiples of a product of a first integer N times the reference clock period of the reference clock signal, the logic values of the comparison indicators in the set of comparison indicators; and
at least one gate configured to logically combine, at lapse of multiples of a product of a second integer P times the reference clock period of the reference clock signal, the logic values stored in the set of flag registers.
18 . The system of claim 11 , wherein the set of comparators is configured to perform the set of comparisons of the measured frequency with each frequency in the set of frequency limit values, and wherein each device further comprises:
a set of logic gates coupled to the set of comparators to receive the set of comparison indicators therefrom, the set of logic gates configured to logically combine, pairwise, comparison indicators in the set of comparison indicators; and
a set of flag registers coupled to the set of logic gates, the set of flag registers configured to store the logic value of each of the pairwise logic combinations of comparison indicators in the set of comparison indicators in respective flag registers of the set of flag registers;
wherein the logic circuitry is configured to produce the global flag signal as a result of at least one of the logic values stored in the set of flag registers having the second logic value.
19 . The system of claim 11 , wherein:
the logic control unit is configured to order the set of frequency limit values in an increasing or decreasing order of limit values;
the set of comparators comprises a pair of comparators configured to perform comparisons of the measured frequency with a respective pair of sequentially adjacent frequency limit values in the ordered set of frequency limit values; and
each device further comprises:
a logic gate coupled to the pair of comparators to receive a pair of comparison indicators therefrom, the logic gate configured to logically combine the pair of comparison indicators;
a set of flag registers coupled to the logic gate, the set of flag registers configured to store the logic value of the logic combination of each pair of comparison indicators in a respective flag register of the set of flag registers; and
wherein the logic circuitry is configured to produce the global flag signal as a result of at least one of the logic values stored in the set of flag registers having the second logic value.
20 . The system of claim 11 , wherein:
the logic control unit is configured to order the set of frequency limit values in increasing or decreasing order of values, and alternately select the upper frequency limit value and the lower frequency limit value;
the set of comparators comprises a comparator that is configured to alternating performing a comparison of the measured frequency with the upper frequency limit value and the lower frequency limit value, respectively; and
each device further comprises a pair of flag registers coupled to the set of comparators and configured to store the logic values of the comparison indicators produced as a result of the alternated comparisons in respective flag registers;
wherein the logic circuitry comprises a logic gate coupled to the pair of flag registers and configured to logically combine the stored logic values.