Neural processor

1. A processing device comprising:

a first set of processors comprising a first processor and a second processor, each of which comprises at least one controllable port;

a first memory operably coupled to the first set of processors;

at least one forward data line configured for one-way transmission of data in a forward direction between the first set of processors; and

at least one backward data line configured for one-way transmission of data in a backward direction between the first set of processors, and

wherein the first set of processors are operably coupled in series via the at least one forward data line and the at least one backward data line,

wherein the first set of processors performs a computation,

a data path for the first set of processors is determined among a plurality of candidate data paths according to a type of the computation, and

the determined data path is configured on the at least one forward data line and the at least one backward data line by controlling controllable ports of the first set of processors.

2. The processing device of claim 1 , wherein a forward data path is configured by turning on a controllable port on the at least one forward data line between the first processor and the second processor and data is transmitted via the forward data path from the first processor to the second processor.

3. The processing device of claim 2 , wherein a backward data path is configured by turning on a controllable port on the at least one backward data line between the first processor the second processor and data is transmitted via the backward data path from the second processor to the first processor.

4. The processing device of claim 1 ,

wherein the determined data path comprises a first and second forward sub-paths configured on the at least one forward data line and a first and second backward sub-paths configured on the at least one backward data line, and

wherein the first forward sub-path is from the first memory to the first processor,

the second forward sub-path is from the first processor to the second processor,

the first backward sub-path is from the second processor to the first processor, and

the second backward sub-path is from the first processor to the first memory.

5. The processing device of claim 4 , wherein the determined data path further comprises a third forward sub-path configured on the at least one forward data line and a third backward sub-path configured on the at least one backward data line,

the third forward sub-path is from the second processor to a second memory, and

the third backward sub-path is from the second memory to the second processor, and

wherein the second memory is the same as or different from the first memory.

6. The processing device of claim 1 ,

wherein a first data path is configured by controlling controllable ports of the first set of processors, the first data path comprises a forward sub-path configured on the at least one forward data line and a backward sub-path configured on the at least one backward data line, the forward sub-path of the first data path is from the first memory to the first processor, and the backward sub-path of the first data path is from the first processor to the first memory,

wherein a second data path is configured by controlling controllable ports of the first set of processors, the second data path comprises a forward sub-path configured on the at least one forward data line and a backward sub-path configured on the at least one backward data line, the backward sub-path of the second data path is from a second memory to the second processor, and the forward sub-path of the second data path is from the second processor to the second memory, and

wherein the second memory is the same as or different from the first memory.

7. The processing device of claim 1 , wherein the determined data path comprises first and second forward sub-paths configured on the at least one forward data line, the first forward sub-path is from the first memory to the first processor, and the second forward sub-path is from the first processor to a second memory, and

wherein the second memory is the same as or different from the first memory.

8. The processing device of claim 1 , wherein the at least one forward data line comprises a plurality of forward data lines, and

some of the plurality of forward data lines are turned off by controlling controllable ports of the first set of processors.

9. The processing device of claim 1 , further comprising:

a second set of processors comprising a third processor and a fourth processor,

wherein the second set of processors are connected in series with each other via a forward data line and a backward data line between the second set of processors.

10. The processing device of claim 9 , further comprising an interconnection through which data are moved,

wherein the first memory, the first set of processors, and the second set of processors are connected to the interconnection, and

data are moved between the first memory, the first set of processors, and the second set of processors via the interconnection.

11. The processing device of claim 1 , further comprising:

at least one first connection line connected to the at least one forward data line and the first processor;

at least one second connection line connected to the at least one backward data line and the first processor;

at least one third connection line connected to the at least one forward data line and the second processor; and

at least one fourth connection line connected to the at least one backward data line and the second processor.

12. The processing device of claim 1 , wherein the first set of processors are included in a system-on-chip, and

the first memory comprises an off-chip memory external to the system-on-chip.

13. The processing device of claim 1 , further comprising:

a second set of processors comprising a third processor and a fourth processor; and

a shared memory shared by the first set of processors and the second set of processors,

wherein the first memory comprises the shared memory.

14. The processing device of claim 1 , wherein controllable ports of the first set of processors are implemented by software or firmware.

15. A processing device comprising:

a first set of processors comprising a first processor, a second processor connected in series with the first processor in a forward direction, and a third processor connected in series with the second processor in the forward direction; and

a first memory connected in series with the first processor in a backward direction,

wherein the first set of processors performs a computation,

a data path for the first set of processors is determined among a plurality of candidate data paths according to a type of the computation,

the determined data path is configured on the at least one forward data line and the at least one backward data line by controlling controllable ports of the first set of processors,

wherein the determined data path comprises a data movement path in the forward direction and a data movement path in the backward direction, and

the determined data path is configured even when at least one of the first processor, the second processor, or the third processor is inoperative.

16. The processing device of claim 15 , wherein if the first processor and the third processor are operative and the second processor is inoperative,

the first processor is provided with first data from the first memory and generates second data by computing the first data,

the second processor is provided with the second data from the first processor and provides the second data to the third processor, and

the third processor is provided with the second data from the second processor and generates third data by computing the second data.

17. The processing device of claim 15 , wherein data lines connecting the first processor to the third processor comprise a plurality of lines, and

all of the plurality of lines are turned on or some of the plurality of lines are turned off according to a bandwidth of data provided from the first memory.

18. The processing device of claim 15 , further comprising:

a fourth processor that is not directly connected to the first processor;

a fifth processor connected in series with the fourth processor in the forward direction; and

an interconnection configured to perform data exchange between the first processor and the fourth processor.

19. A processing device comprising:

a first set of processors comprising a first processor, a second processor connected in series with the first processor in a forward direction, and a third processor connected in series with the second processor in the forward direction; and

a first memory connected in series with the first processor in a backward direction,

wherein the first set of processors performs a computation,

a data path for the first set of processors is determined among a plurality of candidate data paths according to a type of the computation, and

the determined data path is configured in real time on the at least one forward data line and the at least one backward data line by controlling controllable ports of the first set of processors.