Granted Patent B2

US 12,191,857 · App. 18/448,071 · Granted Jan 7, 2025

Inventors: Timothy P Finkbeiner (Boise, ID); Troy D. Larsen (Meridian, ID)

H03K19/1776G06F3/0625G06F3/0688G11C16/26

Abstract

Claims (32)

1. An apparatus, comprising:

a memory device comprising a system processor resident thereon; and

a plurality of memory banks resident on the memory device, wherein at least one memory bank of the plurality of memory banks comprises a bank processor resident thereon;

wherein the system processor is configured to orchestrate execution of processing-in-memory (PIM) instructions by the bank processor of the at least one memory bank without transferring data via an input/output (I/O) interface that couples the memory device to a host.

2. The apparatus of claim 1 , wherein the system processor is a reduced instruction set computer (RISC) processor.

3. The apparatus of claim 2 , wherein the system processor is a RISC-V processor.

4. The apparatus of claim 2 , wherein the bank processor of the at least one memory bank is a RISC-V processor.

5. The apparatus of claim 1 , wherein the system processor is a RISC-V processor having increased processing capability as compared to the bank processor of the at least one memory bank.

6. The apparatus of claim 1 , wherein the at least one memory bank of the plurality of memory banks includes an instruction cache.

7. The apparatus of claim 1 , wherein the at least one memory bank of the plurality of memory banks includes a bank-to-bank transfer cache.

8. The apparatus of claim 1 , wherein the I/O interface is a double date rate (DDR) interface.

9. An apparatus, comprising:

a host;

a memory device coupled to the host and comprising:

a system processor resident on the memory device; and

a plurality of memory banks comprising respective bank processors;

wherein the system processor is configured to orchestrate execution of processing-in-memory (PIM) instructions by the respective bank processors of the plurality of memory banks without transferring data via an input/output (I/O) interface that couples the memory device to the host.

10. The apparatus of claim 9 , further comprising a bank-to-bank transfer bus coupled to the plurality of memory banks via a periphery data path.

11. The apparatus of claim 10 , wherein the memory device comprises a direct memory access (DMA) component coupled to the periphery data path.

12. The apparatus of claim 10 , wherein the bank-to-bank transfer bus provides a data path over which data may be transferred between the plurality of memory banks.

13. The apparatus of claim 9 , wherein the system processor comprises a RISC-V processor.

14. The apparatus of claim 9 , wherein at least one of the respective bank processors comprises a RISC-V processor.

15. The apparatus of claim 9 , wherein the host comprises one or more of a computer, a smartphone, and an internet-of-things device.

16. The apparatus of claim 9 , wherein at least one of the plurality of memory banks includes a number of extended row address components configured to operate as caches for the system processor.

17. An apparatus, comprising:

a host;

a memory device coupled to the host and comprising:

a plurality of memory banks comprising respective bank processors; and

a system processor resident on the memory device, wherein the system processor serves as a supervisory processing device to control operation of the respective bank processors in association with executing a program without transferring data via an input/output (I/O) interface that couples the memory device to the host.

18. The apparatus of claim 17 , wherein the memory device includes an instruction cache configured to store instructions for the system processor.

19. The apparatus of claim 18 , wherein the memory device includes a bank-to-bank transfer cache.

20. The apparatus of claim 18 , wherein the respective bank processors are RISC-V processors and wherein the instruction cache is configured to store RISC-V instructions.

Assignments (1)

Continuity (5)

References Cited (400)