IP Library Granted Patent US 12,640,692
Granted Patent B2
US 12,640,692 · App. 18/449,221 · Granted May 26, 2026

Wideband noise shaping split LNA architecture

Inventors: Emre Ayranci (Costa Mesa, CA); Miles Sanner (San Diego, CA); Anoop Sheokand (Lake Forest, CA); Mengsheng Rui (San Diego, CA)
Assignee: MURATA MANUFACTURING CO., LTD.
H03F3/16H03F1/565H03F2200/294H03F2200/372H03F2200/387
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Quick Facts
Patent No.
US 12,640,692
App. No.
18/449,221
Granted
May 26, 2026
Kind
B2
Abstract

Split low noise amplifier (LNA) architectures providing an improved tradeoff between the noise figure (NF) and the output-to-output isolation are disclosed. The described LNAs include cascode transistors in two amplification paths and an inductive element including a pair of inductors and a common inductor. The inductance values of the inductors and the common inductor can be selected to obtain an improved tradeoff between the NF and isolation while meeting the output matching conditions.

Claims (42)

1 . A low noise amplifier (LNA) comprising:

an input transistor, a first transistor, and a second transistor;

an inductive element comprising a pair of mutually coupled inductors; a first end of the inductive element and drain-terminals of the first and the second transistors being tied together, and a second end of the inductive element being coupled to a bias voltage;

wherein:

the LNA is configured to receive an input signal from an input terminal, and to generate a first output signal at a first output terminal, and a second amplified signal at a second output terminal, the input terminal being coupled to the input transistor; and

inductance values of each inductor of the pair of mutually coupled inductors and a degree of mutual coupling of the pair of mutually coupled inductors are selectable to control noise figure and output-to-output isolation values while maintaining a set output matching condition.

2 . The LNA of claim 1 , wherein inductance values of each mutually coupled inductor of the pair of mutually coupled inductors are equal.

3 . The LNA of claim 1 , wherein the inductive element is a transformer.

4 . The LNA of claim 1 , wherein each of the first and the second transistor are arranged in a cascode configuration with the input transistor.

5 . The LNA of claim 4 , wherein the input transistor, the first transistor and the second transistor are FET transistors.

6 . The LNA of claim 1 , further comprising a third transistor and a fourth transistor, the third transistor coupling the first output terminal to a drain terminal of the first transistor, and the fourth transistor coupling the second output terminal to a drain terminal of the second transistor.

7 . The LNA of claim 6 , wherein a combination of the input transistor, the first transistor, and the third transistor forms a first amplification path of the LNA, and a combination of the input transistor, the second transistor, and the fourth transistor forms a second amplification path of the LNA.

8 . The LNA of claim 7 , wherein the first amplification path and the second amplification path provide equal degree of amplification.

9 . The LNA of claim 6 , wherein the third transistor and the fourth transistor are arranged in a common-source configuration.

10 . The LNA of claim 6 , comprising an input matching network, the input matching network including:

a degenerative inductance coupling a source-terminal of the input transistor to ground, and

a series arrangement of an input inductor and an input capacitor coupling the input terminal to the input transistor.

11 . A low noise amplifier (LNA) comprising:

an input transistor, a first transistor, and a second transistor;

an inductive element comprising:

a first inductor coupled to a drain terminal of the second transistor;

a second inductor coupled to a drain terminal of the third transistor, and

a common inductor tied at a common node together with the first and second inductor,

wherein:

the LNA is configured to receive an input signal from an input terminal, and to generate a first output signal at a first output terminal, and a second amplified signal at a second output terminal, the input terminal being coupled to the input transistor; and

inductance values of the first and the second inductor and the choke inductor are selected to meet desired noise figure and output-to-output isolation values while maintaining a set matching condition.

12 . The LNA of claim 11 , wherein inductance values of the first inductor and the second inductor are equal.

13 . The LNA of claim 11 , wherein each of the first and the second transistor are arranged in a cascode configuration with the input transistor.

14 . The LNA of claim 13 , wherein the input transistor, the first transistor and the second transistor are FET transistors.

15 . The LNA of claim 11 , further comprising a third transistor, and a fourth transistor, the third transistor coupling the first output terminal to a drain terminal of the first transistor, and the fourth transistor coupling the second output terminal to a drain terminal of the second transistor.

16 . The LNA of claim 15 , wherein a combination of the input transistor, the first transistor, and the third transistor forms a first amplification path of the LNA, and a combination of the input transistor, the second transistor, and the fourth transistor forms a second amplification path of the LNA.

17 . The LNA of claim 16 , wherein the first amplification path and the second amplification path provide equal degree of amplification.

18 . The LNA of claim 16 , wherein the third transistor and the fourth transistor are arranged in a common-source configuration.

19 . The LNA of claim 16 , comprising an input matching network, the input matching network including:

a degenerative inductance coupling a source-terminal of the input transistor to ground, and

a series arrangement of an input inductor and an input capacitor coupling the input terminal to the input transistor.

20 . A method of adjusting a noise figure and output-to-output isolation in a low noise split amplifier (LNA), the split LNA comprising:

an input transistor, a first transistor, and a second transistor, wherein the input transistor and the first transistor form a first amplification path, and the input transistor and the second transistor form a second amplification path distinct from the first amplification path; and

an inductive element comprising a pair of mutually coupled inductors; a first end of the inductive element and drain-terminals of the first and the second transistors being tied together,

the method comprising

controlling a coupling factor of the pair of mutually coupled inductors; and

adjusting the noise figure and the output-to-output isolation of the LNA while maintaining a set output matching.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2024
From: PSEMI CORPORATION
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 066753/0987 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2023
From: AYRANCI, EMRE; SANNER, MILES; SHEOKAND, ANOOP; RUI, MENGSHENG
To: PSEMI CORPORATION
Reel/Frame 064903/0107 →
Continuity (2)
Provisional Application 63502202 · May 15, 2023
Related Publication 20240388260A1 · Nov 21, 2024
References Cited (7)
US 10700650B1 · Ayranci et al. · 2020 [cited by applicant]
US 12119797B2 · Cui · 2024 [cited by examiner]
US 20170187338A1 · Wang et al. · 2017 [cited by applicant]
US 20180167040A1 · Sayilir et al. · 2018 [cited by applicant]
US 20240056033A1 · Pehlke · 2024 [cited by examiner]
International Search Report and Written Opinion issued for International PCT Application No. PCT/JP2024/016857 filed on May 2, 2024 on behalf of Murata Manufacturing Co., Ltd. Mail Date: Sep. 4, 2024. 19 pages. [cited by applicant]
Wang, K. et al., “A 22-to-47 Ghz 2-Stage LNA With 22.2 dB Peak Gain by Using Coupled L-Type Interstage Matching Inductors” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, No. 12, Dec. 2020. pp. 460… [cited by applicant]