Command address input buffer bias current reduction
A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.
1 . A memory device comprising:
a memory bank configured to store data; and
command address circuitry configured to regulate access to the memory bank based on command address signals, wherein the command address circuitry comprises a mode of operation selected from a set of modes of operation comprising a first mode of operation and a second mode of operation, wherein the memory device is configured to operate based on a clock signal comprising a plurality of clock cycles and a clock frequency, and wherein the clock frequency in the second mode of operation is greater than or equal to the clock frequency in the first mode of operation,
for a two-cycle command comprising two sets of command address signals that are communicated using two clock cycles of the clock signal:
in response to the mode of operation being the first mode of operation, the command address circuitry is configured to:
when triggered by a chip select signal, read a first set of command address signals of the two sets of command address signals, during a first clock cycle of the clock signal; and
read a second set of command address signals of the two sets of command address signals, immediately subsequent to the first set of command address signals, during a second clock cycle of the clock signal immediately subsequent to the first clock cycle, and
in response to the mode of operation being the second mode of operation, the command address circuitry is configured to:
when triggered by the chip select signal, read the first set of command address signals during the second clock cycle, wherein a third clock cycle of the clock signal is immediately subsequent to the second clock cycle, and
wherein a fourth clock cycle of the clock signal is immediately subsequent to the third clock cycle; and
read the second set of command address signals during the fourth clock cycle,
wherein the command address circuitry comprises an input buffer configured to operate based on a biasing current supplied to the input buffer, and wherein the biasing current in the second mode of operation is different from the biasing current in the first mode of operation.
2 . The memory device of claim 1 , wherein the command address circuitry comprises a command address bus, and wherein the second mode of operation is configured to provide an increased setup-and-hold time on the command address bus, relative to the first mode of operation.
3 . The memory device of claim 1 , wherein the first mode of operation comprises a 1N mode and the second mode of operation comprises a 2N mode.
4 . The memory device of claim 1 , wherein the command address circuitry is configured to default to the second mode of operation in response to initialization of the memory device.
5 . The memory device of claim 4 , wherein the memory device is configured to:
receive a command via a computing system operatively coupled to the memory device; and
change the mode of operation from the second mode of operation to the first mode of operation based on the command.
6 . The memory device of claim 5 , wherein the command is indicative of a user selection of the mode of operation.
7 . The memory device of claim 4 , wherein the memory device is configured to change the mode of operation from the second mode of operation to the first mode of operation based on an assertion of a multi-purpose command (MPC).
8 . The memory device of claim 1 , wherein the biasing current supplied to the input buffer in the second mode of operation is less than the biasing current supplied to the input buffer in the first mode of operation.
9 . The memory device of claim 1 , wherein the memory device is a double data rate type five (DDR5) synchronous dynamic random access memory device.
10 . A memory device comprising:
a memory bank configured to store data; and
command address circuitry configured to regulate access to the memory bank based on sets of command address signals, wherein the command address circuitry is configured to operate in a mode of a set of modes, the set of modes comprising a 1N mode and a 2N mode, wherein the memory device is configured to operate based on a clock signal comprising a plurality of clock cycles and a clock frequency, and wherein the clock frequency in the 2N mode is greater than or equal to the clock frequency in the 1N mode,
for a two-cycle command comprising two sets of command address signals that are communicated using two clock cycles of the clock signal:
in response to operating in the 1N mode, the command address circuitry is configured to:
when triggered by a chip select signal, read a first set of command address signals of the two sets of command address signals, during a first 1N clock cycle of the clock signal; and
read a second set of command address signals of the two sets of command address signals, immediately subsequent to the first set of command address signals, during a second 1N clock cycle of the clock signal immediately subsequent to the first 1N clock cycle, and
in response to operating in the 2N mode, the command address circuitry is configured to:
when triggered by the chip select signal, read the first set of command address signals during a first 2N clock cycle of the clock signal, wherein a second 2N clock cycle of the clock signal is immediately subsequent the first 2N clock cycle; and
read the second set of command address signals during a third 2N clock cycle of the clock signal immediately subsequent to the second 2N clock cycle,
wherein the command address circuitry comprises an input buffer configured to operate based on a biasing current supplied to the input buffer, and wherein the biasing current in the 2N mode of operation is different from the biasing current in the 1N mode of operation.
11 . The memory device of claim 10 , wherein the memory device is configured to default to the 2N mode.
12 . The memory device of claim 10 , wherein the memory device is configured to electrically couple to a computing system comprising a processor, and wherein the memory device is configured to select the mode from the set of modes based on a data signal operatively received from the computing system.
13 . The memory device of claim 12 , wherein the data signal is indicative of a user selection of the mode.
14 . The memory device of claim 10 , wherein the 2N mode is configured to operatively provide an increased setup-and-hold time of the command address circuitry relative to the 1N mode.
15 . A memory device comprising:
a memory bank configured to store data; and
command address circuitry configured to regulate access to the memory bank based on command address signals, wherein the command address circuitry is configured to operate in a mode of a set of modes, the set of modes comprising a first mode and a second mode, wherein the memory device is configured to operate based on a clock signal comprising a plurality of clock cycles and a clock frequency, and wherein the clock frequency in the second mode of operation is greater than or equal to the clock frequency in the first mode of operation,
for a two-cycle command comprising two sets of command address signals that are communicated using two clock cycles of the clock signal:
in response to operating in the first mode, the command address circuitry is configured to:
when triggered by a chip select signal, perform reads of consecutive sets of command address signals of the two sets of command address signals, on immediately consecutive clock cycles, and
in response to operating in the second mode, the command address circuitry is configured to:
when triggered by the chip select signal, perform reads and skip a clock cycle between reads of the consecutive sets of command address signals of the two sets of command address signals,
wherein the command address circuitry comprises an input buffer configured to operate based on a biasing current supplied to the input buffer, and wherein the biasing current in the second mode of operation is different from the biasing current in the first mode of operation.
16 . The memory device of claim 15 , wherein the memory device is configured to initialize in the second mode, and wherein the memory device is configured to, in response to a command received via the command address circuitry, change the mode from the second mode to the first mode.
17 . The memory device of claim 16 , wherein the first mode comprises a 1N mode, wherein the second mode comprises a 2N mode, and wherein the command is indicative of a user selection.
18 . The memory device of claim 15 , wherein the second mode is configured to operatively provide an increased setup-and-hold time of the command address circuitry relative to the first mode.
19 . The memory device of claim 15 , wherein the memory device is a double data rate type five (DDR5) synchronous dynamic random access memory device.
20 . A method comprising:
initializing a memory device in a mode of a set of operating modes, the memory device comprising command address circuitry configured to regulate access to a memory bank of the memory device based on command address signals, wherein the set of operating modes comprises a 2N mode and a 1N mode, wherein the memory device is configured to operate based on a clock signal comprising a plurality of clock cycles and a clock frequency, and wherein the clock frequency in the 2N mode of operation is greater than or equal to the clock frequency in the 1N mode of operation;
for a two-cycle command comprising two sets of command address signals that are communicated using two clock cycles of the clock signal:
reading, via the command address circuitry, a first set of command address signals of the two sets of command address signals, during a first clock cycle of the clock signal; and
reading, via the command address circuitry, a second set of command address signals of the two sets of command address signals, immediately subsequent to the first set of command address signals, wherein reading the second set of command address signals comprises:
in response to operating in the 1N mode, reading the second set of command address signals during a second clock cycle of the clock signal immediately subsequent to the first clock cycle; and
in response to operating in the 2N mode, reading the second set of command address signals during a third clock cycle of the clock signal immediately subsequent to the second clock cycle, wherein a chip select signal is used for triggering reading the first set of command address signals in the 1N mode and the 2N mode,
wherein the command address circuitry comprises an input buffer configured to operate based on a biasing current supplied to the input buffer, and wherein the biasing current in the 2N mode of operation is different from the biasing current in the 1N mode of operation.
21 . The method of claim 20 , wherein initializing the memory device in the mode comprises initializing the memory device in the 2N mode, the method comprising:
receiving, via the command address circuitry, a command; and
in response to the command, changing the mode of the memory device from the 2N mode to the 1N mode.
22 . The method of claim 21 , wherein the command comprises a multi-purpose command (MPC) to operate the memory device in the 1N mode.
23 . The method of claim 20 , wherein the 2N mode is configured to operatively provide an increased setup-and-hold time of the command address circuitry relative to the 1N mode.
24 . The method of claim 20 , wherein the memory device is a double data rate type five (DDR5) synchronous dynamic random access memory device.