Vertical Nano-Pillar Transistor Structures for 3-D ICS
Nano-pillar field-effect transistor (FET) structure that include one or more of the following characteristics: vertical device structure and vertical current flow; vertically displaced source and drain regions; different nanowire/nanosheet geometries and dimensions for different nano-pillar embodiments; and/or body contacts made through wide nano-pillar structures. In addition, by utilizing layer transfer techniques, direct access to drain contacts of a nano-pillar FET structure is available, which enables a significant improvement in transistor performance (e.g., lower R ON resistance, faster switching speed). An additional advantage of the novel nano-pillar FET structures is that available top and bottom contacts may be used in various 3-D integrated circuit structures, such as by using layer transfer and/or hybrid bonding.
1 . A vertical nano-pillar field-effect transistor (FET), including:
(a) a handle wafer; and
(b) an inverted nano-pillar FET including a superstructure bonded to a surface of the handle wafer.
2 . The invention of claim 1 , wherein the inverted nano-pillar FET includes:
(a) one or more nano-pillar structures each having a first end, a middle portion, and a second end;
(b) at least one source cap, each source cap in electrical contact with the first end of an associated nano-pillar structure of the one or more nano-pillar structures;
(c) a gate layer surrounding the middle portion of the one or more nano-pillar structures;
(d) a drain region in electrical contact with the second end of the one or more one nano-pillar structures.
3 . The invention of claim 2 , wherein the drain region is diffused across the second end of one or more nano-pillar structures.
4 . The invention of claim 2 , wherein the drain region is not diffused across the second end of the one or more nano-pillar structures.
5 . The invention of claim 4 , further including at least one body contact connected to an undiffused region near the drain-side end of at least one of the one or more nano-pillars.
6 . The invention of claim 2 , wherein the one or more nano-pillar structures include at least one nanowire structure.
7 . The invention of claim 2 , wherein the one or more nano-pillar structures include at least one nanosheet structure.
8 . The invention of claim 2 , wherein the one or more nano-pillar structures include at least two nanosheet structures spanned by a common fin-like nanosheet.
9 - 20 . [Canceled]
21 . A vertical nano-pillar field-effect transistor (FET), including:
(a) a handle wafer; and
(b) an inverted nano-pillar FET including a superstructure bonded to a surface of the handle wafer, wherein the inverted nano-pillar FET includes:
(1) one or more nano-pillar structures each having a first end, a middle portion, and a second end;
(2) at least one source cap, each source cap in electrical contact with the first end of an associated nano-pillar structure of the one or more nano-pillar structures;
(3) a gate layer surrounding the middle portion of the one or more nano-pillar structures;
(4) a drain region in electrical contact with the second end of the one or more one nano-pillar structures, wherein the drain region is not diffused across the second end of the one or more nano-pillar structures.
22 . The invention of claim 20 , wherein the one or more nano-pillar structures include at least one nanowire structure.
23 . The invention of claim 20 , wherein the one or more nano-pillar structures include at least one nanosheet structure.
24 . The invention of claim 20 , wherein the one or more nano-pillar structures include at least two nanosheet structures spanned by a common fin-like nanosheet.
25 . The invention of claim 20 , wherein the one or more nano-pillar structures comprised silicon.
26 . The invention of claim 20 , further including:
(a) a first dielectric layer formed around the one or more nano-pillars between the at least one source cap and the gate layer; and
(b) a second dielectric layer formed around the one or more nano-pillars between the gate layer and the drain region.
27 . A vertical nano-pillar field-effect transistor (FET), including:
(a) a handle wafer; and
(b) an inverted nano-pillar FET including a superstructure bonded to a surface of the handle wafer, wherein the inverted nano-pillar FET includes:
(1) one or more nano-pillar structures each having a first end, a middle portion, and a second end;
(2) at least one source cap, each source cap formed on and in electrical contact with the first end of an associated nano-pillar structure of the one or more nano-pillar structures;
(3) a gate layer surrounding the middle portion of the one or more nano-pillar structures;
(4) at least one drain cap, each drain cap formed on and in electrical contact with the second end of an associated nano-pillar structure of the one or more nano-pillar structures.
28 . The invention of claim 27 , wherein the one or more nano-pillar structures include at least one nanowire structure.
29 . The invention of claim 27 , wherein the one or more nano-pillar structures include at least one nanosheet structure.
30 . The invention of claim 27 , wherein the one or more nano-pillar structures include at least two nanosheet structures spanned by a common fin-like nanosheet.
31 . The invention of claim 27 , wherein the one or more nano-pillar structures comprised silicon.
32 . The invention of claim 27 , further including:
(a) a first dielectric layer formed around the one or more nano-pillars between the at least one source cap and the gate layer; and
(b) a second dielectric layer formed around the one or more nano-pillars between the gate layer and the at least one drain cap.
33 - 39 . [Canceled]