TRANSISTOR-LEVEL SYNTHESIS
The technology involves transistor-level synthesis for integrated circuit design and fabrication. According to one aspect, a computer-implemented method performs transistor-level synthesis for an integrated circuit element. This includes generating single-stage transistor networks from Boolean functions, in which each single-stage transistor network is composed of a pulldown network and a pullup network. The single-stage transistor networks are scaled to multi-stage transistor networks to globally optimize for factored form literals. Technology mapping can then be performed based on the factored form literals to generate a circuit design.
1 . A computer-implemented method to perform transistor-level synthesis for an integrated circuit element, the method comprising:
generating, by one or more processors of a computer system, single-stage transistor networks from Boolean functions, wherein each single-stage transistor network is composed of a pulldown network and a pullup network;
scaling, by the one or more processors, the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals; and
performing, by the one or more processors, technology mapping based on the factored form literals to generate a circuit design.
2 . The method of claim 1 , wherein generating the single-stage transistor networks includes:
representing a function to be performed by the integrated circuit element as a sum-of-products (SOP); and
finding a factorization that minimizes a number of the factored form literals.
3 . The method of claim 2 , wherein finding the factorization includes performing one of algebraic or Boolean factoring.
4 . The method of claim 3 , wherein the Boolean factoring generates a solution represented as an AND-OR graph, in which factored forms are generated for both the function to be performed and a complement of the function to be performed.
5 . The method of claim 3 , wherein finding the factorization includes creating an AND-OR graph for each transistor topology corresponding to the factored form literals.
6 . The method of claim 1 , wherein generating the single-stage transistor networks comprises generating an irredundant sum-of-products (ISOP) from a truth table.
7 . The method of claim 1 , wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes And-inverter graph (AIG) rewriting for the factored form literals.
8 . The method of claim 7 , wherein the AIG rewriting includes replacing a part of a circuit component using one or more precomputed smaller structures that are smaller than the circuit component.
9 . The method of claim 7 , wherein the AIG uses size as a cost function to limit a number of AIG nodes.
10 . The method of claim 1 , wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes And-inverter graph (AIG) resubstitution for the factored form literals.
11 . The method of claim 1 , wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes performing refactoring.
12 . The method of claim 11 , wherein refactoring includes rewriting maximum fanout-free cones (MFFCs) with a new factored implementation when a number of gates decreases.
13 . The method of claim 1 , wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes performing technology mapping driven by the factored form literals.
14 . A computing system, comprising:
memory configured to store integrated circuit information; and
one or more processors operatively coupled to the memory, the one or more processors being configured to:
generate single-stage transistor networks from Boolean functions, wherein each single-stage transistor network is composed of a pulldown network and a pullup network;
scale the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals; and
perform technology mapping based on the factored form literals to generate a circuit design.
15 . The computing system of claim 14 , wherein the one or more processors are further configured to store the circuit design in the memory.
16 . The computing system of claim 14 , wherein generation of the single-stage transistor networks includes:
representation of a function to be performed by an integrated circuit element as a sum-of-products (SOP); and
find a factorization that minimizes a number of the factored form literals.
17 . The computing system of claim 14 , wherein generation of the single-stage transistor networks comprises generation of an irredundant sum-of-products (ISOP) from a truth table.
18 . The computing system of claim 14 , wherein the single-stage transistor networks are scaled to multi-stage transistor networks to globally optimize for factored form literals by performance of And-inverter graph (AIG) rewriting for the factored form literals.
19 . The computing system of claim 14 , wherein the single-stage transistor networks are scaled to multi-stage transistor networks to globally optimize for factored form literals by performance of And-inverter graph (AIG) resubstitution for the factored form literals.
20 . The computing system of claim 14 , wherein the single-stage transistor networks are scaled to multi-stage transistor networks to globally optimize for factored form literals by performance of refactoring.