CHANNEL SIZING FOR INTER-KERNEL COMMUNICATION
Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.
1 . A tangible, non-transitory, machine-readable-medium, comprising machine readable instructions to:
access a high level program comprising instructions to implement a design on an integrated circuit;
convert the high level program into a low level program to be implemented on the integrated circuit;
identify a first kernel, a second kernel, and an inter-kernel channel based on the low level program or based on the high level program, wherein the first kernel writes data to the inter-kernel channel and the second kernel reads the data from the inter-kernel channel;
identify a potential stall due to expected writes to the inter-kernel channel by the first kernel, an indication of expected reads from the inter-kernel channel by the second kernel, or both,
wherein the expected writes of the inter-kernel channel comprises, during a first cycle, the first kernel writing to the inter-kernel channel, and, during a second cycle, the first kernel not writing to the inter-kernel channel, and
wherein the expected reads of the inter-kernel channel comprises, during a third cycle, the second kernel reading from the inter-kernel channel, and, during a fourth cycle, the second kernel not reading from the inter-kernel channel;
modify a size of the inter-kernel channel, based on a determination of a number of elements to be held in the inter-kernel channel to prevent the potential stall when the first kernel writes more elements to the inter-kernel channel than the second kernel reads or the second kernel reads more elements from the inter-kernel channel than the first kernel writes,
wherein the size is based on the expected writes of the inter-kernel channel, the expected reads of the inter-kernel channel, or both; and
provide one or more kernels and the inter-kernel channel corresponding to the low level program for implementation on the integrated circuit, wherein the one or more kernels include the first and second kernels.
2 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the inter-kernel channel comprises a first-in, first-out buffer.
3 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the instructions are further to: identify, via the compiler, a second inter-kernel channel, wherein the first kernel writes to the second inter-kernel channel, and the second kernel reads from the second inter-kernel channel.
4 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the size of the inter-kernel channel comprises a depth of the inter-kernel channel.
5 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein inter-kernel channel comprises at least one control signal, and wherein the at least one control signal is provided to the first kernel, the second kernel, or both.
6 . The tangible, non-transitory, machine-readable medium of claim 5 , wherein the at least one control signal comprises a not full signal that indicates whether a buffer of the inter-kernel channel is full.
7 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the instructions are further to identify the potential stall, wherein the potential stall would occur because a buffer of the inter-kernel channel is full.
8 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the instructions are further to identify the potential stall, wherein the potential stall would occur because a buffer of the inter-kernel channel is empty.
9 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the first cycle and the fourth cycle occur simultaneously, and the second cycle and the third cycle occur simultaneously.
10 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the low level program provided for storage on the integrated circuit has the modified size of the inter-kernel channel.
11 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the expected writes comprises an indication of a predication of the expected writes.
12 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the expected writes comprises an indication of performance of conditional branches containing the expected writes.
13 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the expected reads comprises an indication of a predication of the expected writes.
14 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the expected writes comprises an indication of performance of conditional branches containing the expected reads.
15 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the potential stall would be caused due to predication of the expected writes or the expected reads.
16 . The tangible, non-transitory, machine-readable medium of claim 1 , wherein the modification of the size of the inter-kernel channel is based at least in part on predication of the expected writes, the expected reads, or both.
17 . A system, comprising:
an integrated circuit;
memory storing instructions; and
a processor to execute the instructions to:
implement a compiler;
access, via the compiler, a high level program comprising instructions to implement a design on the integrated circuit;
convert, via the compiler, the high level program into a low level program to be implemented on the integrated circuit;
identify, via the compiler, a first kernel, a second kernel, and an inter-kernel channel based on the low level program or based on the high level program, wherein the first kernel writes data to the inter-kernel channel and the second kernel reads the data from the inter-kernel channel;
identify, via the compiler, a potential stall due to expected writes to the inter-kernel channel by the first kernel, expected reads from the inter-kernel channel by the second kernel, or both,
wherein the expected writes of the inter-kernel channel comprises, during a first cycle, the first kernel writing to the inter-kernel channel, and, during a second cycle, the first kernel not writing to the inter-kernel channel, and
wherein the expected reads of the inter-kernel channel comprises, during a third cycle, the second kernel reading from the inter-kernel channel, and, during a fourth cycle, the second kernel not reading from the inter-kernel channel;
modify, via the compiler, a size of the inter-kernel channel, based on a determination of a number of elements to be held in the inter-kernel channel to prevent the expected stall when the first kernel writes more elements to the inter-kernel channel than the second kernel reads or the second kernel reads more elements from the inter-kernel channel than the first kernel writes,
wherein the size is based on the expected writes of the inter-kernel channel, the expected reads of the inter-kernel channel, or both; and
provide, via the compiler, one or more kernels and the inter-kernel channel corresponding to the low level program for implementation on the integrated circuit, wherein the one or more kernels comprise the first kernel and the second kernel.
18 . The system of claim 17 , wherein the integrated circuit comprises a field-programmable, gate array.
19 . The system of claim 17 , wherein the compiler is part of a design software package executed by the processor.
20 . The system of claim 17 , wherein the instructions are further to identify the potential stall, wherein the potential stall would occur because a buffer of the inter-kernel channel is empty or full.