FET fin and vertical nanosheet formation using porous semiconductors
Structures and corresponding methods of fabrication for ICs having fins and/or vertical nanosheets made by forming and etching a porous semiconductor (π-Semi) from a crystalline semiconductor. Embodiments include FinFETs and “gate-all-around” FETs. Such FET structures may be made by patterning an IC die to outline one or more regions of crystalline semiconductor material in the outline of a fin or nanosheet; converting the outlined regions to π-Semi having essentially vertical walls; further converting the outlined regions to π-Semi having flared walls; then selecting one of these options: etching the π-Semi to define fins, etching the π-Semi to define nanosheets with a residual π-Semi floor, or etching the π-Semi to define nanosheets with no residual π-Semi floor; and forming a gate structure over the fins or around the nanosheets. Additional steps and structures (e.g., formation of source and drain regions, formation of contacts, metallization layers, vias, etc.) may then be performed.
1 . A method of fabricating a FinFET, including:
(a) patterning an IC die to outline one or more regions of crystalline semiconductor material in the outline of a fin;
(b) converting the one or more outlined regions of crystalline semiconductor to porous semiconductor (π-Semi) having essentially vertical walls to a selected depth d;
(c) further converting the one or more outlined regions of crystalline semiconductor below the selected depth d to π-Semi having flared walls;
(d) etching the π-Semi to define fins;
(e) forming a gate structure over the fins.
2 . The method of claim 1 , further including fabricating a source and a drain adjacent the gate structure.
3 . The method of claim 2 , further including fabricating electrical contacts to the source, gate, and drain.
4 . The method of claim 3 , further including fabricating a superstructure on the IC die.
5 . The method of claim 1 , wherein the crystalline semiconductor material is one of silicon, germanium, or a silicon-germanium alloy.
6 . A method of fabricating a gate-all-around FET, including:
(a) patterning an IC die to outline one or more regions of crystalline semiconductor material in the outline of a nanosheet;
(b) converting the one or more outlined regions of crystalline semiconductor to porous semiconductor (π-Semi) having essentially vertical walls to a selected depth d;
(c) further converting the outlined regions of crystalline semiconductor below the selected depth d to π-Semi having flared walls;
(d) etching the π-Semi to define nanosheets with no residual π-Semi floor;
(e) forming a gate structure around the nanosheets.
7 . The method of claim 6 , further including fabricating a source and a drain adjacent the gate structure.
8 . The method of claim 7 , further including fabricating electrical contacts to the source, gate, and drain.
9 . The method of claim 8 , further including fabricating a superstructure on the IC die.
10 . The method of claim 6 , wherein the crystalline semiconductor material is one of silicon, germanium, or a silicon-germanium alloy.
11 . A method of fabricating a gate-all-around FET, including:
(a) patterning an IC die to outline one or more regions of crystalline semiconductor material in the outline of a nanosheet;
(b) converting the one or more outlined regions of crystalline semiconductor to porous semiconductor (π-Semi) having essentially vertical walls to a selected depth d;
(c) further converting the one or more outlined regions of crystalline semiconductor below the selected depth d to π-Semi having flared walls;
(d) etching the π-Semi to define nanosheets with a residual π-Semi floor;
(e) forming a gate structure around the nanosheets.
12 . The method of claim 11 , further including fabricating a source and a drain adjacent the gate structure.
13 . The method of claim 12 , further including fabricating electrical contacts to the source, gate, and drain.
14 . The method of claim 13 , further including fabricating a superstructure on the IC die.
15 . The method of claim 11 , wherein the crystalline semiconductor material is one of silicon, germanium, or a silicon-germanium alloy.
16 . A field-effect transistor, including:
(a) a region of crystalline semiconductor material including a source region and a drain region;
(b) at least one vertical fin of the crystalline semiconductor material spanning between the source region and the drain region, the at least one vertical fin having a top, sidewalls, and a bottom;
(c) a gate structure overlaying the top and sidewalls of the at least one vertical fin between the source region and the drain region; and
(d) a porous semiconductor region separating the bottom of the at least one vertical fin from other underlying regions.
17 . The field-effect transistor of claim 16 , wherein the crystalline semiconductor material is one of silicon, germanium, or a silicon-germanium alloy.
18 . A field-effect transistor, including:
(a) a region of crystalline semiconductor material including a source region and a drain region;
(b) at least one vertical nanosheet of the crystalline semiconductor material spanning horizontally between the source region and the drain region, the at least one vertical nanosheet having a top, vertical sidewalls, and a bottom;
(c) a gate structure surrounding the top, vertical sidewalls, and bottom of the at least one vertical nanosheet between the source region and the drain region; and
(d) a porous semiconductor region separating the bottom of the at least one vertical nanosheet from other underlying regions.
19 . The field-effect transistor of claim 18 , wherein the crystalline semiconductor material is one of silicon, germanium, or a silicon-germanium alloy.