IP Library Granted Patent US 12,455,603
Granted Patent B2
US 12,455,603 · App. 18/475,001 · Granted Oct 28, 2025

Universal serial bus power delivery (USB-PD)

Inventors: Arun Khamesra (Bangalore, IN); Hariom Rai (Bangalore, IN); Soon Hwei Tan (Singapore, SG)
Assignee: Cypress Semiconductor Corporation
G06F1/266G06F1/3215G06F1/3253G06F1/3287H02M1/0032G06F2213/0042
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Quick Facts
Patent No.
US 12,455,603
App. No.
18/475,001
Granted
Oct 28, 2025
Kind
B2
Abstract

A method of operating a Universal Serial Bus Power Delivery (USB-PD) power converter includes responsive to detecting an absence of a load device sending a low power mode signal from a secondary-side controller, coupled to control a secondary-side of the USB-PD power converter, to a primary-side controller coupled to control a primary-side of the USB-PD power converter, and transitioning the secondary-side controller from a secondary-side active mode to a secondary-side low power mode, transitioning the primary-side controller from a primary-side active mode to a primary-side low power mode responsive to receiving the low power mode signal, responsive to detecting a connection of the load device sending an active mode signal from the secondary-side controller to the primary-side controller, and transitioning the secondary-side controller from the secondary-side low power mode to the secondary-side active mode, and transitioning the primary-side controller from the primary-side low power mode to the primary-side active mode.

Claims (106)

1. A Universal Serial Bus Power Delivery (USB-PD) system comprising:

a transformer comprising a primary-side coupled to receive a rectified alternating current (AC) input voltage at an input port, and a secondary-side connected to provide a direct current (DC) output voltage at an output port;

a first power switch connected to the primary-side;

a second power switch connected between the input port and the primary-side;

a primary-side controller coupled to the first power switch to control operation of the transformer;

a gate driver connected between the second power switch and the primary-side controller, wherein the primary-side controller is configured to:

transition from a primary-side active mode to a primary-side low power mode responsive to receiving a low power mode signal;

power down the gate driver in the primary-side low power mode; and

transition from the primary-side low power mode to the primary-side active mode responsive to receiving an active mode signal; and

a secondary-side controller coupled to the output port, wherein the secondary-side controller configured to:

responsive to detecting an absence of a load device on the output port, send the low power mode signal to the primary-side controller and transition from a secondary-side active mode to a secondary-side low power mode; and

responsive to detecting a connection of the load device to the output port, transition from the secondary-side low power mode to the secondary-side active mode and send the active mode signal to the primary-side controller.

2. The USB-PD system of claim 1 , wherein:

the primary-side controller comprises a detector communicatively coupled to the secondary-side controller;

the detector is configured in a differential configuration in the primary-side active mode to detect the low power mode signal; and

the detector is configured in a single ended configuration in the primary-side low power mode to detect the active mode signal.

3. The USB-PD system of claim 2 , wherein:

the detector detects the low power mode signal using a positive reference signal and a negative reference signal in the differential configuration; and

the detector detects the active mode signal using a ground reference signal in the single ended configuration.

4. The USB-PD system of claim 2 , comprising:

a pulse transformer coupled between the secondary-side controller and the detector of the primary-side controller.

5. The USB-PD system of claim 1 , comprising:

a pull-up transistor connected between a power voltage source and a power terminal of the gate driver, wherein:

the primary-side controller comprises a pull-down transistor connected between a gate terminal of the pull-up transistor and a reference voltage source;

the primary-side controller is configured to assert an enable signal at a gate terminal of the pull-down transistor in the primary-side active mode; and

the primary-side controller is configured to remove the enable signal in the primary-side low power mode.

6. The USB-PD system of claim 1 , comprising:

a filter connected between a gate terminal of the second power switch and a source terminal of the second power switch.

7. The USB-PD system of claim 1 , wherein:

the secondary-side controller configured to:

transition to a secondary-side wake-up mode;

responsive to a voltage on the output port being less than a first threshold in the secondary-side wake-up mode, send a wake-up signal to the primary-side controller and send a drive signal to the primary-side controller; and

responsive to the voltage on the output port being greater than a second threshold, send the low power mode signal to the primary-side controller and return to the secondary-side low power mode; and

the primary-side controller is configured to:

responsive to receiving the wake-up signal, transition to a primary-side wake-up mode and control the first power switch based on the drive signal; and

responsive to receiving the low power mode signal, returning to the primary-side low power mode.

8. The USB-PD system of claim 1 , comprising:

an across-the-line capacitor (X-cap) coupled between the input port and the primary-side, wherein:

the secondary-side controller is configured to:

periodically transition from the secondary-side low power mode to a secondary-side wake-up mode; and

send a wake-up signal to the primary-side controller in the secondary-side wake-up mode for each transition, and

the primary-side controller is configured to:

transition to a primary-side wake-up mode responsive to receiving the wake-up signal;

detect in the primary-side wake-up mode a low voltage condition at the input port; and

discharge the X-cap responsive to detecting a predetermined number of low voltage conditions.

9. The USB-PD system of claim 1 , wherein:

a power consumption of the transformer, the primary-side controller in the primary-side low power mode, and the secondary-side controller in the secondary-side low power mode is less than 5 mW.

10. A method of operating a Universal Serial Bus Power Delivery (USB-PD) power converter comprising:

responsive to detecting an absence of a load device on an output port of the USB-PD power converter:

sending a low power mode signal from a secondary-side controller, coupled to control a secondary-side of the USB-PD power converter, to a primary-side controller coupled to control a primary-side of the USB-PD power converter; and

transitioning the secondary-side controller from a secondary-side active mode to a secondary-side low power mode;

transitioning the primary-side controller from a primary-side active mode to a primary-side low power mode responsive to receiving the low power mode signal;

responsive to detecting a connection of the load device to the output port:

sending an active mode signal from the secondary-side controller to the primary-side controller; and

transitioning the secondary-side controller from the secondary-side low power mode to the secondary-side active mode;

transitioning the primary-side controller from the primary-side low power mode to the primary-side active mode responsive to receiving the active mode signal;

controlling an active clamp flyback (ACF) circuit coupled to the primary-side using a gate driver coupled to the primary-side controller in the primary-side active mode; and

powering down the gate driver in the primary-side low power mode.

11. The method of claim 10 , comprising:

configuring a detector in the primary-side controller in a differential configuration in the primary-side active mode to detect the low power mode signal; and

configuring the detector in a single ended configuration in the primary-side low power mode to detect the active mode signal.

12. The method of claim 11 , wherein:

detecting the low power mode signal comprises detecting the low power mode signal using a positive reference signal and a negative reference signal in the differential configuration; and

detecting the active mode signal comprises detecting the active mode signal using a ground reference signal in the single ended configuration.

13. The method of claim 11 , comprising:

communicating the active mode signal and the low power mode signal using a pulse transformer coupled between the secondary-side controller and the detector of the primary-side controller.

14. The method of claim 10 , comprising:

asserting, in the in the primary-side active mode, an enable signal at a gate terminal of a pull-down transistor connected between a gate terminal of a pull-up transistor and a reference voltage source, wherein the pull-up transistor is connected between a power voltage source and a power terminal of the gate driver; and

removing the enable signal in the primary-side low power mode.

15. The method of claim 10 , comprising:

maintaining an off state of the ACF circuit in the primary-side low power mode.

16. The method of claim 10 , comprising:

transitioning the secondary-side controller to a secondary-side wake-up mode;

responsive to a voltage on the output port being less than a first threshold, sending a wake-up signal to the primary-side controller in the secondary-side wake-up mode and sending a drive signal to the primary-side controller;

transitioning the primary-side controller to a primary-side wake-up mode responsive to receiving the wake-up signal;

controlling operation of a transformer of the USB-PD power converter by the primary-side controller based on the drive signal in the primary-side wake-up mode;

responsive to the voltage on the output port being greater than a second threshold, sending the low power mode signal to the primary-side controller and returning the secondary-side controller to the secondary-side low power mode; and

returning the primary-side controller to the primary-side low power mode responsive to receiving the low power mode signal.

17. The method of claim 10 , comprising:

periodically transitioning from the secondary-side low power mode to a secondary-side wake-up mode;

sending a wake-up signal to the primary-side controller in the secondary-side wake-up mode for each transition to the secondary-side wake-up mode;

transitioning the primary-side controller to a primary-side wake-up mode responsive to receiving the wake-up signal;

detecting, in the primary-side wake-up mode, a low voltage condition at an input port of the USB-PD power converter; and

responsive to detecting a predetermined number of low voltage conditions, discharging an across-the-line capacitor (X-cap) coupled between the input port and the primary-side of the transformer.

18. The method of claim 10 , wherein:

after transitioning the secondary-side controller from the secondary-side active mode to the secondary-side low power mode and transitioning the primary-side controller from the primary-side active mode to the primary-side low power mode a power consumption of a transformer coupled between the primary side and the secondary side, the primary-side controller, and the secondary-side controller is less than 5 mW.

19. A Universal Serial Bus Power Delivery (USB-PD) system comprising:

a transformer comprising a primary-side coupled to receive a rectified alternating current (AC) input voltage at an input port, and a secondary-side connected to provide a direct current (DC) output voltage at an output port;

a first power switch connected between the input port and the primary-side;

a second power switch connected between the output port and the secondary-side;

an across-the-line capacitor (X-cap) coupled between the input port and the primary-side;

a primary-side controller coupled to the first power switch; and

a secondary-side controller coupled to the second power switch, wherein:

the secondary-side controller is configured to, responsive to detecting an absence of a load device on the output port, send a low power mode signal to the primary-side controller and transition from a secondary-side active mode to a secondary-side low power mode;

the primary-side controller is configured to transition from a primary-side active mode to a primary-side low power mode responsive to receiving the low power mode signal;

the secondary-side controller is configured to, responsive to detecting a connection of the load device to the output port, transition from the secondary-side low power mode to a secondary-side active mode and send an active mode signal to the primary-side controller;

the primary-side controller is configured to transition from the primary-side low power mode to a primary-side active mode responsive to receiving the active mode signal;

the secondary-side controller is configured to:

periodically transition from the secondary-side low power mode to a secondary-side wake-up mode; and

send a wake-up signal to the primary-side controller in the secondary-side wake-up mode for each transition, and

the primary-side controller is configured to:

transition to a primary-side wake-up mode responsive to receiving the wake-up signal;

detect, in the primary-side wake-up mode, a low voltage condition at the input port; and

discharge the X-cap responsive to detecting a predetermined number of low voltage conditions.

20. The USB-PD system of claim 19 , wherein:

a power consumption of the transformer, the primary-side controller in the primary-side low power mode, and the secondary-side controller in the secondary-side low power mode is less than 5 mW.

Assignments (2)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2024
From: KHAMESRA, ARUN; RAI, HARIOM; TAN, SOON HWEI
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 068697/0805 →
Continuity (1)
Related Publication 20250103119A1 · Mar 27, 2025
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