ENVELOPE DETECTOR ARCHITECTURE WITH NOISE CANCELATION
According to an embodiment, an envelope detector circuit for detecting an envelope of a signal from a sensor in a pre-amplifier circuit of a hard disk drive is provided. The circuit includes a half-wave rectifier, a low-pass filter, and a differential full-wave rectifier. The half-wave rectifier receives a differential voltage from the sensor indicating a fly height of the hard disk drive and generates a pair of single-ended output waveforms based on the differential voltage. Each pair of single-ended output waveforms has a positive polarity for a half-cycle it passes through. The low-pass filter includes a first and a second low-pass filter. The low-pass filter allows low-frequency signals from the pair of single-ended output waveforms to pass through while attenuating or blocking higher-frequency signals. The differential full-wave rectifier reconstructs a differential signal from the low-pass filter while removing DC rectified components.
1 . An envelope detector circuit for detecting an envelope of a signal from a sensor in a pre-amplifier circuit of a hard disk drive, the envelope detector circuit comprising:
a half-wave rectifier configured to:
receive a differential voltage from the sensor indicating a fly height of the hard disk drive, and
generate a pair of single-ended output waveforms based on the differential voltage, each of the pair of single-ended output waveforms having a positive polarity for a half-cycle it passes through;
a low-pass filter comprising a first low-pass filter and a second low-pass filter, the low-pass filter being configured to allow low-frequency signals from the pair of single-ended output waveforms to pass through while attenuating or blocking higher-frequency signals; and
a differential full-wave rectifier configured to reconstruct a differential signal from the low-pass filter while removing DC rectified components.
2 . The envelope detector circuit of claim 1 , wherein the low-pass filter is a second-order low-pass filter, and wherein a cut-off frequency of the low-pass filter is adjustable.
3 . The envelope detector circuit of claim 1 , further comprising a gain stage circuit coupled to an output terminal of the differential full-wave rectifier, the gain stage circuit being configured to amplify an output signal of the differential full-wave rectifier.
4 . The envelope detector circuit of claim 3 , wherein a gain value of the gain stage circuit is selectable from a range of gain values.
5 . The envelope detector circuit of claim 1 , wherein the half-wave rectifier comprises:
a comparator configured to generate a binary signal based on a difference between a singled-ended positive side of the differential voltage at a non-inverted terminal of the comparator and a single-ended negative side of the differential voltage at an inverted terminal of the comparator;
an inverter configured to invert the binary signal from the comparator to generate an inverted binary signal;
a first buffer configured to receive the singled-ended positive side of the differential voltage;
a second buffer configured to receive the single-ended negative side of the differential voltage;
a first resistor coupled to an output terminal of the first buffer;
a second resistor coupled to an output terminal of the second buffer, the first resistor and the second resistor coupled at a common node having a common-mode voltage;
a first transistor configured to pass through an output signal of the first buffer at a first output terminal of the half-wave rectifier based on the binary signal;
a second transistor configured to pass through the common-mode voltage at the first output terminal of the half-wave rectifier based on the inverted binary signal;
a third transistor configured to pass through an output signal of the second buffer at a second output terminal of the half-wave rectifier based on the inverted binary signal; and
a fourth transistor configured to pass through the common-mode voltage at the second output terminal of the half-wave rectifier based on the binary signal.
6 . The envelope detector circuit of claim 1 , wherein the differential full-wave rectifier comprises:
a comparator configured to generate a binary signal based on a difference between a singled-ended positive-side of the differential voltage at a non-inverted terminal of the comparator and a singled-ended negative-side of the differential voltage at an inverted terminal of the comparator;
an inverter configured to invert the binary signal from the comparator to generate an inverted binary signal;
a first buffer coupled to a first output of the low-pass filter configured to receive a first filtered signal of a first single-ended signal of the pair of single-ended output waveforms;
a second buffer coupled to a second output of the low-pass filter configured to receive a second filtered signal of a second single-ended signal of the pair of single-ended output waveforms;
a first transistor configured to pass through an output signal of the first buffer at a first output terminal of the differential full-wave rectifier based on the binary signal;
a second transistor configured to pass through the output signal of the first buffer at a second output terminal of the differential full-wave rectifier based on the inverted binary signal;
a third transistor configured to pass through an output signal of the second buffer at the second output terminal of the differential full-wave rectifier based on the binary signal; and
a fourth transistor configured to pass through the output signal of the second buffer at the first output terminal of the differential full-wave rectifier based on the inverted binary signal.
7 . The envelope detector circuit of claim 1 , wherein the differential signal reconstructed from the low-pass filter is used to operate the hard disk drive.
8 . A pre-amplifier circuit of a hard disk drive, the pre-amplifier circuit comprising:
a sensor configured to measure a fly height of the hard disk drive;
a half-wave rectifier configured to:
receive a differential voltage from the sensor indicating the fly height of the hard disk drive, and
generate a pair of single-ended output waveforms based on the differential voltage, each of the pair of single-ended output waveforms having a positive polarity for a half-cycle it passes through;
a low-pass filter comprising a first low-pass filter and a second low-pass filter, the low-pass filter being configured to allow low-frequency signals from the pair of single-ended output waveforms to pass through while attenuating or blocking higher-frequency signals; and
a differential full-wave rectifier configured to reconstruct a differential signal from the low-pass filter while removing DC rectified components.
9 . The pre-amplifier circuit of claim 8 , wherein the low-pass filter is a second-order low-pass filter, and wherein a cut-off frequency of the low-pass filter is adjustable.
10 . The pre-amplifier circuit of claim 8 , further comprising a gain stage circuit coupled to an output terminal of the differential full-wave rectifier, the gain stage circuit being configured to amplify an output signal of the differential full-wave rectifier.
11 . The pre-amplifier circuit of claim 10 , wherein a gain value of the gain stage circuit is selectable from a range of gain values.
12 . The pre-amplifier circuit of claim 8 , wherein the half-wave rectifier comprises:
a comparator configured to generate a binary signal based on a difference between a singled-ended positive side of the differential voltage at a non-inverted terminal of the comparator and a singled-ended negative side of the differential voltage at an inverted terminal of the comparator;
an inverter configured to invert the binary signal from the comparator to generate an inverted binary signal;
a first buffer configured to receive the singled-ended positive side of the differential voltage;
a second buffer configured to receive the singled-ended negative side of the differential voltage;
a first resistor coupled to an output terminal of the first buffer;
a second resistor coupled to an output terminal of the second buffer, the first resistor and the second resistor coupled at a common node having a common-mode voltage;
a first transistor configured to pass through an output signal of the first buffer at a first output terminal of the half-wave rectifier based on the binary signal;
a second transistor configured to pass through the common-mode voltage at the first output terminal of the half-wave rectifier based on the inverted binary signal;
a third transistor configured to pass through an output signal of the second buffer at a second output terminal of the half-wave rectifier based on the inverted binary signal; and
a fourth transistor configured to pass through the common-mode voltage at the second output terminal of the half-wave rectifier based on the binary signal.
13 . The pre-amplifier circuit of claim 8 , wherein the differential full-wave rectifier comprises:
a comparator configured to generate a binary signal based on a difference between a singled-ended positive side of the differential voltage at a non-inverted terminal of the comparator and a singled-ended negative side of the differential voltage at an inverted terminal of the comparator;
an inverter configured to invert the binary signal from the comparator to generate an inverted binary signal;
a first buffer coupled to a first output of the low-pass filter configured to receive a first filtered signal of a first single-ended signal of the pair of single-ended output waveforms;
a second buffer coupled to a second output of the low-pass filter configured to receive a second filtered signal of a second single-ended signal of the pair of single-ended output waveforms;
a first transistor configured to pass through an output signal of the first buffer at a first output terminal of the differential full-wave rectifier based on the binary signal;
a second transistor configured to pass through the output signal of the first buffer at a second output terminal of the differential full-wave rectifier based on the inverted binary signal;
a third transistor configured to pass through an output signal of the second buffer at the second output terminal of the differential full-wave rectifier based on the binary signal; and
a fourth transistor configured to pass through the output signal of the second buffer at the first output terminal of the differential full-wave rectifier based on the inverted binary signal.
14 . The pre-amplifier circuit of claim 8 , wherein the differential signal reconstructed from the low-pass filter is used to operate the hard disk drive.
15 . A method for detecting an envelope of a signal from a sensor in a pre-amplifier circuit of a hard disk drive, the method comprising:
receiving, by a half-wave rectifier, a differential voltage from the sensor indicating a fly height of the hard disk drive;
generating, by the half-wave rectifier, a pair of single-ended output waveforms based on the differential voltage, each of the pair of single-ended output waveforms having a positive polarity for a half-cycle it passes through;
filtering, by a low-pass filter, high-frequency signals from the pair of single-ended output waveforms while passing through low-frequency signals; and
reconstructing, by a differential full-wave rectifier, a differential signal from the low-pass filter while removing DC rectified components.
16 . The method of claim 15 , wherein the low-pass filter is a second-order low-pass filter, and wherein a cut-off frequency of the low-pass filter is adjustable.
17 . The method of claim 15 , further comprising amplifying, by a gain stage circuit, an output signal of the differential full-wave rectifier.
18 . The method of claim 17 , wherein a gain value of the gain stage circuit is selectable from a range of gain values.
19 . The method of claim 15 , further comprising:
generating, by a comparator of the half-wave rectifier, a binary signal based on a difference between a singled-ended positive side of the differential voltage at a non-inverted terminal of the comparator and a singled-ended negative side of the differential voltage at an inverted terminal of the comparator;
inverting, by an inverter of the half-wave rectifier, the binary signal from the comparator to generate an inverted binary signal;
receiving, by a first buffer of the half-wave rectifier, the single-ended positive side of the differential voltage;
receiving, by a second buffer of the half-wave rectifier, the single-ended negative side of the differential voltage, wherein a first resistor is coupled to an output terminal of the first buffer, a second resistor is coupled to an output terminal of the second buffer, the first resistor and the second resistor coupled at a common node having a common-mode voltage;
passing through, by a first transistor of the half-wave rectifier, an output signal of the first buffer at a first output terminal of the half-wave rectifier based on the binary signal;
passing through, by a second transistor of the half-wave rectifier, the common-mode voltage at the first output terminal of the half-wave rectifier based on the inverted binary signal;
passing through, by a third transistor of the half-wave rectifier, an output signal of the second buffer at a second output terminal of the half-wave rectifier based on the inverted binary signal; and
passing through, by a fourth transistor of the half-wave rectifier, the common-mode voltage at the second output terminal of the half-wave rectifier based on the binary signal.
20 . The method of claim 15 , further comprising:
generating, by a comparator of the differential full-wave rectifier, a binary signal based on a difference between a single-ended positive side of the differential voltage at a non-inverted terminal of the comparator and a single-ended negative side of the differential voltage at an inverted terminal of the comparator;
inverting, by an inverter of the differential full-wave rectifier, the binary signal from the comparator to generate an inverted binary signal;
receiving, by a first buffer of the differential full-wave rectifier, a first filtered signal of a first single-ended signal of the pair of single-ended output waveforms;
receiving, by a second buffer of the differential full-wave rectifier, a second filtered signal of a second single-ended signal of the pair of single-ended output waveforms;
passing through, by a first transistor of the differential full-wave rectifier, an output signal of the first buffer at a first output terminal of the differential full-wave rectifier based on the binary signal;
passing through, by a second transistor of the differential full-wave rectifier, the output signal of the first buffer at a second output terminal of the differential full-wave rectifier based on the inverted binary signal;
passing through, by a third transistor of the differential full-wave rectifier, an output signal of the second buffer at the second output terminal of the differential full-wave rectifier based on the binary signal; and
passing through, by a fourth transistor of the differential full-wave rectifier, the output signal of the second buffer at the first output terminal of the differential full-wave rectifier based on the inverted binary signal.