Utilizing a single chip select line to support multiple peripheral components in a synchronous serial communication system
A synchronous serial communication controller, a synchronous serial communication peripheral component, and a computer-implemented method enabling synchronous serial communication between the synchronous serial communication controller and the synchronous serial communication peripheral component are provided. The example synchronous serial communication controller includes a serial communication interface, configured with a clock logic wire, a data output logic wire, a data input logic wire, and a shared select line logic wire. The shared select line logic wire is electrically connected to a plurality of peripheral components. A selected peripheral component of the plurality of peripheral components is indicated by chip identification data transmitted on the data output logic wire.
1 . A synchronous serial communication controller comprising:
a serial communication interface, comprising:
a clock logic wire;
a data output logic wire;
a data input logic wire;
a dedicated chip select logic wire electrically connected exclusively between a legacy peripheral component and the synchronous serial communication controller, wherein serial communication data intended for the legacy peripheral component is indicated exclusively based on an asserted state of the dedicated chip select logic wire; and
a shared select line logic wire electrically connected to a plurality of peripheral components, wherein serial communication with a selected peripheral component of the plurality of peripheral components is initiated by transmission of a notification opcode followed by chip identification data transmitted on the data output logic wire.
2 . The serial communication controller of claim 1 , wherein a voltage on the shared select line logic wire is driven low to indicate to the selected peripheral component a transmission of the chip identification data.
3 . The serial communication controller of claim 1 , wherein the serial communication interface is electrically connected to a serial peripheral interface (SPI) bus.
4 . The serial communication controller of claim 3 , wherein the shared select line logic wire is a chip select logic wire.
5 . The serial communication controller of claim 1 , wherein the legacy peripheral component is selected by driving an electrical signal on the dedicated chip select logic wire low.
6 . A synchronous serial communication system comprising:
a synchronous serial communication peripheral component comprising:
a first serial communication interface, comprising:
a clock logic wire;
a data output logic wire;
a data input logic wire; and
a shared select line logic wire electrically connected to a plurality of peripheral components, wherein serial communication with a selected peripheral component of the plurality of peripheral components is initiated by reception of a notification opcode followed by chip identification data received on the shared select line logic wire; and
a synchronous serial communication legacy peripheral component comprising:
a second serial communication interface comprising:
the clock logic wire;
the data output logic wire;
the data input logic wire; and
a dedicated chip select logic wire electrically connected exclusively between a legacy peripheral component and a synchronous serial communication controller, wherein serial communication data intended for the legacy peripheral component is indicated exclusively based on an asserted state of the dedicated chip select logic wire.
7 . The synchronous serial communication system of claim 6 , wherein the shared select line logic wire is activated to indicate to the synchronous serial communication peripheral component a transmission of the chip identification data.
8 . The synchronous serial communication system of claim 6 , wherein the first serial communication interface of the synchronous serial communication peripheral component is electrically connected to a serial peripheral interface (SPI) bus.
9 . The synchronous serial communication system of claim 8 , wherein the shared select line logic wire is a chip select logic wire.
10 . The synchronous serial communication system of claim 6 , wherein in an instance in which the notification opcode is not recognized by the synchronous serial communication peripheral component, the synchronous serial communication peripheral component is configured to perform one or more actions in accordance with an operation opcode.
11 . The synchronous serial communication system of claim 6 , wherein the synchronous serial communication peripheral component further comprises a local chip identifier, wherein the local chip identifier is compared to the chip identification data to determine receipt of a subsequent operation opcode and data bytes.
12 . A computer-implemented method for synchronous serial communication between a serial communication controller and a plurality of peripheral components, the computer-implement method comprising:
initiating serial communication with a selected peripheral component of the plurality of peripheral components by transmitting a notification opcode followed by chip identification data on a data output logic wire of a serial communication interface,
wherein the serial communication interface comprises:
a clock logic wire;
the data output logic wire;
a data input logic wire;
a dedicated chip select logic wire electrically connected exclusively between a legacy peripheral component and the serial communication controller, wherein serial communication data intended for the legacy peripheral component is indicated exclusively based on an asserted state of the dedicated chip select logic wire; and
a shared select line logic wire; and
transmitting an operation opcode indicating an operation related to the selected peripheral component.
13 . The computer-implemented method of claim 12 , further comprising:
activating the shared select line logic wire to indicate to the plurality of peripheral components the transmission of the notification opcode.
14 . The computer-implemented method of claim 12 , wherein the serial communication interface is electrically connected to a serial peripheral interface (SPI) bus.
15 . The computer-implemented method of claim 12 , further comprising:
exchanging one or more data bytes with the selected peripheral component.