Gateway for connection to a host processor and multiple slaves and method for operating the gateway
A gateway for connection to a host processor and multiple slaves, which are organized in a point-to-point (P2P) topology, is provided. The gateway has an independent channel for each of the slaves, and the gateway can receive multiple control signals, each including at least one control signal for a particular predetermined slave from the multiple slaves, from the host processor. The host processor determines whether the slaves for which the at least one control signal has been received are in an operational state; and to simultaneously output the control signals received from the host processor to the slaves for which the at least one control signal has been received only when all of the slaves for which the at least one control signal has been received are in the operational state.
1. A gateway for connection to a host processor and multiple slaves, the gateway and the slaves being organized in a point-to-point (P2P) topology such that the gateway has an independent channel for each of the slaves, the gateway being configured to:
receive multiple control signals, each control signal including at least one control signal for a particular predetermined slave from the multiple slaves, from the host processor;
determine whether the slaves for which the at least one control signal has been received are in an operational state; and
simultaneously output the control signals received from the host processor to the slaves for which the at least one control signal has been received only when all of the slaves for which the at least one control signal has been received are in the operational state, wherein the gateway comprises:
a first interface for communication with the host processor by means of a first communication standard;
a second interface for communication with the slaves by means of a second communication standard; and
a memory connected to the first and/or to the second interface for the purpose of temporarily storing data that are received at the gateway via the first and/or the second interface,
wherein the memory is protected by means of an error detection method and/or an error correction method.
2. The gateway as claimed in claim 1 , wherein
the first interface is configured to generate a first error correction code based on data received at the first interface and to output the generated first error correction code to the memory together with the data received at the first interface, and/or
the second interface is configured to take data received at the second interface as a basis for generating a second error correction code and to output the generated second error correction code to the memory together with the data received at the second interface.
3. The gateway as claimed in claim 2 , wherein
the memory is configured to use the first error correction code received at the memory to detect, and optionally correct, an error in the data received from the first interface, and/or
the memory is configured to use the second error correction code received at the memory to detect, and optionally correct, an error in the data received from the second interface.
4. The gateway as claimed in claim 2 , wherein
the memory is configured to output the received first error correction code to the second interface together with the data received from the first interface, and the second interface is configured to use the first error correction code received at the second interface to detect, and optionally correct, an error in the data received at the second interface from the memory, and/or
the memory is configured to output the received second error correction code to the first interface together with the data received from the second interface, and the first interface is configured to use the second error correction code received at the first interface to detect, and optionally correct, an error in the data received at the first interface from the memory.
5. The gateway as claimed in claim 4 , wherein
the gateway has a control unit that is connected to the first and/or the second interface via the memory,
the memory is configured to output the received first error correction code to the second interface via the control unit together with the data received from the first interface, and
the control unit is configured to use the first error correction code received at the control unit to detect, and optionally correct, an error in the data received at the control unit from the memory.
6. A method for operating a gateway for connection to a host processor and multiple slaves, the gateway and the slaves being organized in a point-to-point (P2P) topology such that the gateway has an independent channel for each of the slaves, the gateway being configured to:
receive multiple control signals, each control signal including at least one control signal for a particular predetermined slave from the multiple slaves, from the host processor;
determine whether the slaves for which the at least one control signal has been received are in an operational state; and
simultaneously output the control signals received from the host processor to the slaves for which the at least one control signal has been received only when all of the slaves for which the at least one control signal has been received are in the operational state, wherein the gateway includes:
a first interface for communication with the host processor by means of a first communication standard;
a second interface for communication with the slaves by means of a second communication standard; and
a memory connected to the first and/or to the second interface for the purpose of temporarily storing data that are received at the gateway via the first and/or the second interface,
wherein the memory is protected by means of an error detection method and/or an error correction method, the method comprising:
receiving multiple control signals, each comprising at least one control signal for a particular predetermined slave from the multiple slaves, at the gateway from the host processor;
determining whether the slaves for which the at least one control signal has been received are in an operational state;
simultaneously outputting the control signals received from the host processor to the slaves for which the at least one control signal has been received only when all of the slaves for which the at least one control signal has been received are in the operational state; and
protecting data received by means of the first and/or the second interface by means of an error detection method and/or an error correction method at the first interface, the second interface and/or the memory.