IP Library Granted Patent US 12,347,813
Granted Patent B2
US 12,347,813 · App. 18/490,270 · Granted Jul 1, 2025

Semiconductor package and related methods

Inventors: Chee Hiong Chew (Seremban, MY); Erik Nino Tolentino (Seremban, MY); Vemmond Jeng Hung Ng (Senawang, MY); Shutesh Krishnan (Seremban, MY)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L25/072H01L23/3735H01L24/40H01L24/84H01L25/18H01L25/50H01L2224/4001H01L2224/40137H01L2224/4052H01L2224/40991H01L2224/8484H01L2224/84931H01L2924/01029H01L2924/01047H01L2924/0503H01L2924/1203H01L2924/13055
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Quick Facts
Patent No.
US 12,347,813
App. No.
18/490,270
Granted
Jul 1, 2025
Kind
B2
Abstract

Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.

Claims (36)

1. A method of forming a semiconductor package comprising:

applying sintering material over one of a first side of a plurality of die or a first side of a clip;

applying sintering material to one of a first side of an electrically conductive spacer or the clip;

pressure sintering the electrically conductive spacer and plurality of die to the clip through the sintering material;

applying sintering material to one of a the second side of the plurality of die or a substrate, the second side of the plurality of die opposite the first side of the plurality of die;

applying sintering material to one of a second side of the electrically conductive spacer or the substrate, the second side opposite the first side of the electrically conductive spacer; and

pressure sintering the substrate to the electrically conductive spacer and plurality of die through the sintering material.

2. The method of claim 1 , wherein the plurality of die and the electrically conductive spacer are flipped after they are pressure sintered to the clip, after which the plurality of die and the electrically conductive spacer are then pressure sintered to the substrate.

3. The method of claim 1 , further comprising etching the clip.

4. The method of claim 1 , wherein the substrate comprises a direct bonded copper (DBC) substrate.

5. The method of claim 1 , wherein the plurality of die and the electrically conductive spacer are pressure sintered to the clip after the plurality of die and the electrically conductive spacer are pressure sintered to the substrate.

6. The method of claim 1 , wherein the sintering material comprises silver sintering material.

7. A method of forming a semiconductor package comprising:

providing a clip comprising a first portion with a first thickness and a second portion with a second thickness less than the first thickness;

after the clip is provided, directly coupling one or more die to the first portion through one of a conductive adhesive or a solder;

directly coupling an electrically conductive spacer to the second portion through one of the conductive adhesive or the solder; and

coupling a substrate to the one or more die and the electrically conductive spacer;

wherein the clip electrically couples the one or more die and the electrically conductive spacer;

wherein one of the clip is simultaneously coupled directly to the one or more die and the electrically conductive spacer through one of the conductive adhesive or the solder or the substrate is simultaneously coupled to the one or more die and the electrically conductive spacer after the one or more die and the electrically conductive spacer are coupled to the clip.

8. The method of claim 7 , wherein the electrically conductive spacer is a vertical connection system.

9. The method of claim 7 , wherein the one of the conductive adhesive or the solder comprises a silver sintering material.

10. The method of claim 7 , wherein the one or more die comprise an insulative gate bipolar transistor (IGBT) and a diode.

11. The method of claim 7 , wherein the electrically conductive spacer comprises a copper foil.

12. The method of claim 7 , wherein the package includes only a single clip.

13. The method of claim 7 , wherein the electrically conductive spacer is directly coupled to both the substrate and the clip through one of the conductive adhesive or the solder.

14. The method of claim 7 , wherein the one or more die comprise a plurality of die, wherein the plurality of die comprises varying thicknesses.

15. A method of forming a semiconductor package comprising:

coupling one or more die over a substrate;

coupling an electrically conductive spacer over the substrate;

directly coupling a redistribution layer (RDL) comprising boron nitrite simultaneously over the one or more die and the electrically conductive spacer through one of a conductive adhesive or a solder;

wherein the RDL electrically connects the one or more die and the electrically conductive spacer.

16. The method of claim 15 , wherein the electrically conductive spacer is directly coupled to both the substrate and the RDL through a silver sinter material.

17. The method of claim 15 , wherein the RDL comprises a plurality of electrical traces on one side.

18. The method of claim 15 , wherein the electrically conductive spacer comprises copper foil.

19. The method of claim 15 , wherein the electrically conductive spacer comprises a thickness equal to a thickness of a die of the one or more die.

20. The method of claim 15 , wherein the substrate comprises a direct bonded copper (DBC) substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2023
From: TOLENTINO, ERIK NINO MERCADO; CHEW, CHEE HIONG; NG, VEMMOND JENG HUNG; KRISHNAN, SHUTESH
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 065281/0345 →