Radio frequency doubler
In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.
1. A frequency doubler comprising:
a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source, wherein the current source is configured to provide a bias current, and wherein a second terminal of the current source is connected to a supply potential;
a third transistor connected between a second differential output and the first terminal of the current source; and
a feedback loop configured to control a first voltage to a gate of the first transistor, a second voltage to a gate of the second transistor and a third voltage to a gate of the third transistor based on a difference between DC components of the first and second differential outputs,
wherein the feedback loop comprises a first input coupled to the first differential output, a second input coupled to the second differential output and an output configured to provide an output voltage, and
wherein the feedback loop further comprises:
an operational amplifier;
a capacitor connected between a non-inverting input of the amplifier and the supply potential;
a capacitor connected between an inverting input of the amplifier and an output of the amplifier;
a first resistor coupling the non-inverting input to the first input of the feedback loop; and
a second resistor coupling the inverting input to the second input of the feedback loop,
wherein, in a first implementation, the first input of the feedback loop is coupled to the first differential output and the second input of the feedback loop is coupled to the second differential output for controlling the third voltage, and
wherein, in a second implementation, the first input of the feedback loop is coupled to the second differential output and the second input of the feedback loop is coupled to the first differential output for controlling the first and second voltages.
2. The frequency doubler of claim 1 , further comprising a circuit configured to:
provide, at a first output of the circuit, the first voltage being based on the output voltage of the feedback loop when the first voltage is controllable by the feedback loop;
provide, at a second output of the circuit, the second voltage being based on the output voltage of the feedback loop when the second voltage is controllable by the feedback loop; and
provide, at a third output of the circuit, a constant voltage as the third voltage.
3. The frequency doubler of claim 2 , wherein the circuit further comprises:
a first capacitor coupling a first differential input to the gate of the first transistor; and
a second capacitor coupling a second differential input to the gate of the second transistor.
4. The frequency doubler of claim 3 , wherein the circuit further comprises:
a first resistor coupling the gate of the first transistor to a first node configured to receive the output voltage of the feedback loop; and
a second resistor coupling the gate of the second transistor to the first node.
5. The frequency doubler of claim 4 , wherein the circuit further comprises a third capacitor coupling the first node to the supply potential.
6. The frequency doubler of claim 2 , wherein the circuit further comprises a transformer having its primary coupled to the first and second differential inputs, and its secondary coupled to the gates of the first and second transistors, the secondary being configured to be biased by the output voltage of the feedback loop.
7. The frequency doubler of claim 1 , further comprising a circuit configured to:
provide, at a first output of the circuit, a constant voltage as the first voltage;
provide, at a second output of the circuit, the constant voltage as the second voltage; and
provide, at a third output of the circuit, the third voltage being based on the output voltage of the feedback loop when the third voltage is controllable by the feedback loop.
8. The frequency doubler of claim 7 , wherein the circuit further comprises:
a first capacitor coupling a first differential input to the gate of the first transistor; and
a second capacitor coupling a second differential input to the gate of the second transistor.
9. The frequency doubler of claim 7 , wherein the circuit further comprises:
a first resistor coupling the gate of the first transistor to a first node configured to receive the output voltage of the feedback loop; and
a second resistor coupling the gate of the second transistor to the first node.
10. The frequency doubler of claim 9 , wherein the circuit further comprises a third capacitor coupling the first node to the supply potential.
11. The frequency doubler of claim 7 , wherein the circuit further comprises a fourth capacitor and a second node between the third output and a third input of the circuit, and wherein the fourth capacitor couples the second node to the supply potential.
12. The frequency doubler of claim 1 , wherein the first and second transistors are identical N-channel MOS transistors.
13. The frequency doubler of claim 12 , wherein the third transistor is an N-channel MOS transistor identical to the first and second transistors.
14. A frequency doubler comprising:
a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source, wherein the current source is configured to provide a bias current, and wherein a second terminal of the current source is connected to a supply potential;
a third transistor connected between a second differential output and the first terminal of the current source; and
a feedback loop configured to control a first voltage to a gate of the first transistor or a second voltage to a gate of the second transistor based on a difference between DC components of the first and second differential outputs, wherein the feedback loop comprises a first input coupled to the second differential output, a second input coupled to the first differential output and an output configured to provide an output voltage, and
wherein the feedback loop further comprises:
an operational amplifier;
a capacitor connected between a non-inverting input of the amplifier and the supply potential;
a capacitor connected between an inverting input of the amplifier and an output of the amplifier;
a first resistor coupling the inverting input to the first input of the feedback loop; and
a second resistor coupling the non-inverting input to the second input of the feedback loop, wherein the first and second voltages are controllable by the output voltage.
15. The frequency doubler of claim 14 , further comprising a circuit configured to:
provide, at a first output of the circuit, the first voltage based on the output voltage of the feedback loop;
provide, at a second output of the circuit, the second voltage based on the output voltage of the feedback loop; and
provide, at a third output of the circuit, a constant voltage as a third voltage to a gate of the third transistor.
16. The frequency doubler of claim 15 , wherein the circuit further comprises:
a first capacitor coupling a first differential input to the gate of the first transistor; and
a second capacitor coupling a second differential input to the gate of the second transistor.
17. The frequency doubler of claim 16 , wherein the circuit further comprises:
a first resistor coupling the gate of the first transistor to a first node, the first node configured to receive the output voltage of the feedback loop;
a second resistor coupling the gate of the second transistor to the first node; and
a third capacitor coupling the first node to the supply potential.
18. A frequency doubler comprising:
a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source, wherein the current source is configured to provide a bias current, and wherein a second terminal of the current source is connected to a supply potential;
a third transistor connected between a second differential output and the first terminal of the current source; and
a feedback loop configured to control a third voltage to a gate of the third transistor based on a difference between DC components of the first and second differential outputs,
wherein the feedback loop comprises a first input coupled to the first differential output, a second input coupled to the second differential output and an output configured to provide an output voltage, and
wherein the feedback loop comprises:
an operational amplifier;
a capacitor connected between a non-inverting input of the amplifier and the supply potential;
a capacitor connected between an inverting input of the amplifier and an output of the amplifier;
a first resistor coupling the inverting input to the first input of the feedback loop; and
a second resistor coupling the non-inverting input to the second input of the feedback loop, wherein the third voltage is controllable by the output voltage.
19. The frequency doubler of claim 18 , further comprising a circuit configured to:
provide, at a first output of the circuit, a constant voltage to a gate of the first transistor;
provide, at a second output of the circuit, the constant voltage to the gate of the second transistor; and
provide, at a third output of the circuit, the third voltage based on the output voltage of the feedback loop.
20. The frequency doubler of claim 19 , wherein the circuit further comprises:
a first capacitor coupling a first differential input to the gate of the first transistor; and
a second capacitor coupling a second differential input to the gate of the second transistor.