Secondary side controlled flyback converter with accurate feed-forward sensing
A flyback-converter with synchronous-rectifier (SR) sense architecture is provided. A secondary side controller includes a SR-sense pin coupled through an external resistor to a drain of an SR on the secondary-side, a negative-sensing-detector, a peak-detector, a zero-crossing-detector, all coupled to the pin, and a resistor network (Rn) coupled between the pin and ground. The Rn includes a first resistor (R 1 ) to couple the pin and to ground through a first switch (S 1 ) during negative-sensing to divide a voltage (V SR_drain ) coupled to the pin, and a second, higher resistance resistor (R 2 ) to couple the pin to ground through a second switch (S 2 ) during peak-detection to divide V SR_drain coupled to the pin. S 1 and S 2 are controlled by register-transfer-level circuit in the SSC. A line-feed-forward (LFF) circuit is coupled to the pin through an active diode to receive an undivided V SR_drain and mirrors diode current to control the converter in LFF mode.
1 . A secondary side controller (SSC) for a flyback converter, the SSC comprising:
a SR sense (SR_SEN) pin coupled through an external resistor (Rext) to a drain (SR_drain) of a synchronous rectifier (SR) on a secondary side of the flyback converter;
a negative-sensing-detector (NSN), a peak-detector (PKD), and a zero-crossing detector (ZCD) coupled to the SR_SEN pin; and
a resistor network (Rn) coupled between the SR_SEN pin and ground, wherein the Rn comprises:
a first resistor (R 1 ) coupled to the SR_SEN pin and through a first switch (S 1 ) to ground, the first switch controlled by a control negative sense (CTRLN) signal from an register transfer level (RTL) circuit in the SSC, the first switch operable to couple the R 1 to ground based on an expected time of an NSN event to divide a SR_drain voltage (V SR_drain ) coupled to the SR_SEN pin; and
a second resistor (R 2 ) having a resistance greater than the R 1 coupled to the SR_SEN pin and through a second switch (S 2 ) to ground, the second switch controlled by a control peak sense (CTRLP) signal from the RTL circuit, the second switch operable to couple the R 2 to ground during peak detection to divide the V SR_drain coupled to the SR_SEN pin, and to decouple the R 2 after a pre-defined number of peaks have been detected.
2 . The SSC of claim 1 further comprising a line-feed-forward (LFF) circuit coupled to the SR_SEN pin through an active diode, wherein the RTL circuit is operable to remove the CTRLN signal from S 1 and CTRLP signal from S 2 to decouple R 1 and R 2 from ground so that an undivided V SR_drain is coupled through Rext to a voltage (V SR_SEN ) on the SR_SEN pin during a feed-forward sensing mode of the flyback converter.
3 . The SSC of claim 2 wherein the active diode is operable to remove from V SR_SEN on the SR_SEN pin a component of V SR_Drain arising from a output bus voltage (V BUS ) on an output of the secondary side of the flyback converter.
4 . The SSC of claim 3 wherein the active diode is further operable to clamp the SR_SEN pin to V BUS when R 1 and R 2 are decoupled from ground.
5 . The SSC of claim 4 wherein the active diode comprises a pair of drain extended p-type field effect transistors (DEPFETs) coupled at source terminals thereof and connected in series between the SR_SEN pin and the LFF circuit, the pair of DEPFETs operated using dynamic bulk switching provided by a third DEPFET with a drain terminal coupled to the SR_SEN pin and a source terminal coupled to a bulk terminal of the DEPFET coupled to the SR_SEN pin, and wherein gate terminals of all DEPEFETs are coupled to V BUS .
6 . The SSC of claim 2 wherein a diode current (I D ) through the active diode is mirrored by the LFF circuit and used for feed-forward sensing.
7 . The SSC of claim 6 wherein the LFF circuit further comprises a sample and hold (S/H) circuit to sample and hold the I D , and wherein the LFF circuit is operable to generate a feed-forward current (I_feedfwd) from the ID, and to extract information from the I_feedfwd on a line-in voltage (V IN ) applied to a primary side of the flyback converter, and to generate feed-forward (FF) signals used by the secondary side controller to control the flyback converter during feed-forward sensing mode.
8 . The SSC of claim 7 wherein the LFF circuit further comprises a multiplier coupled between the active diode and the S/H circuit, the multiplier operable to multiply the Ip based on a turns-ratio (N) of a transformer in the flyback converter, to generate I_feedfwd that is independent of the transformer's turns-ratio.
9 . The SSC of claim 8 wherein the LFF circuit further comprises a compensation current (I_COMP) source, and wherein the LFF circuit is further operable to add I_COMP to the sampled Ip to compensate for a diode voltage (V D ) dropped across the active diode.
10 . The SSC of claim 9 wherein the LFF circuit is further operable to compare the I_feedfwd generated to a number of predefined current references and to detect over-voltage and under-voltage conditions of V IN .
11 . The SSC of claim 6 wherein the LFF circuit further comprises an internal clamping circuit I_feedfwd to a predetermined value to provide a minimum I_feedfwd current for V IN lower than 80V.
12 . A flyback converter comprising:
a transformer including a primary winding coupled between a line-in voltage (V IN ) and through a power switch (PS) to ground, and a secondary winding coupled between an output bus voltage (V BUS ) and through a synchronous rectifier (SR) to ground; and
secondary side controller (SSC) comprising:
a SR sense (SR_SEN) pin coupled through an external resistor (Rext) to the secondary winding and a drain (SR_drain) of the SR;
a negative-sensing-detector (NSN), a peak-detector (PKD), and a zero-crossing detector (ZCD) coupled to the SR_SEN pin; and
a resistor network (Rn) coupled between the SR_SEN pin and ground, wherein the Rn comprises:
a first resistor (R 1 ) coupled to the SR_SEN pin and through a first switch (S 1 ) to ground, the first switch controlled by a control negative sense (CTRLN) signal from an register transfer level (RTL) circuit in the SSC, the first switch operable to couple the R 1 to ground based on an expected time of an NSN event to divide a SR_drain voltage (V SR_drain ) coupled to the SR_SEN pin; and
a second resistor (R 2 ) having a resistance greater than the R 1 coupled to the SR_SEN pin and through a second switch (S 2 ) to ground, the second switch controlled by a control peak sense (CTRLP) signal from the RTL circuit, the second switch operable to couple the R 2 to ground during peak detection to divide the V SR_drain coupled to the SR_SEN pin, and to decouple the R 2 after a pre-defined number of peaks have been detected.
13 . The flyback converter of claim 12 wherein the SSC further comprises a line-feed-forward (LFF) circuit coupled to the SR_SEN pin through an active diode, wherein the RTL circuit is operable to remove the CTRLN signal from S 1 and CTRLP signal from S 2 to decouple R 1 and R 2 from ground so that an undivided V SR_drain is coupled through Rext to a voltage (V SR_SEN ) on the SR_SEN pin during a feed-forward sensing mode of the flyback converter.
14 . The flyback converter of claim 13 wherein the active diode is operable to remove from V SR_SEN on the SR_SEN pin a component of V SR_Drain arising from V BUS , and is further operable to clamp the SR_SEN pin to V BUS when R 1 and R 2 are decoupled from ground.
15 . The flyback converter of claim 13 wherein the LFF circuit is operable to generate a feed-forward current (I_feedfwd) from a diode current (I D ) through the active diode, and to extract information from the I_feedfwd on V IN to generate feed-forward (FF) signals used by the SSC to control the flyback converter during feed-forward sensing mode.
16 . A method of operating a secondary side controller for a flyback converter, the method comprising:
coupling an undivided voltage (V SR_Drain ) on a drain of a synchronous rectifier (SR) on a secondary side of a transformer in the flyback converter through an external resistor (Rext) to a synchronous rectifier sense (SR_SEN) pin of the secondary side controller, V SR_Drain comprising a sum of a line-in voltage (V IN ) applied to a primary side of the transformer multiplied by a turns-ratio (N) of the transformer and a voltage (V BUS ) on an output bus coupled to the secondary side;
coupling a voltage (V SR_SEN ) on the SR_SEN pin to a line feed forward (LFF) circuit through an active diode, the active diode operable to remove from the V SR_SEN a component of V SR_Drain arising from V BUS ;
in the LFF circuit, sampling and holding a diode current (I D ) through the active diode and generating a feed-forward current (I_feedfwd); and
extracting information from the I_feedfwd on V IN and generating feed-forward (FF) signals used by the secondary side controller to control the flyback converter.
17 . The method of claim 16 further comprising before sampling and holding I D , multiplying ID using a multiplier based on the turns-ratio (N) of the transformer, to generate I_feedfwd that is independent of transformer's turns-ratio.
18 . The method of claim 17 wherein generating I_feedfwd comprises adding a compensation current (I_COMP) to the sampled I D to compensate for a voltage drop (VD) across the active diode.
19 . The method of claim 18 further comprising comparing the I_feedfwd generated against a number of predefined current references to detect over-voltage and under-voltage condition of V IN .
20 . The method of claim 19 wherein generating I_feedfwd comprises clamping I_feedfwd to a predetermined value to provide a minimum I_feedfwd current for V IN lower than 80V.