LINEAR DECIMATION FILTERS FOR INCREMENTAL DELTA-SIGMA ANALOG TO DIGITAL CONVERTERS

1 . A device, comprising:

a data rate signal input:

a digital signal input:

a weight generator connected to the digital signal input to generate a weight signal via a weight signal output:

an adder having a digital signal output, a first addition input connected to the weight signal output, and a second addition input connected to the digital signal output: and

an AND-gate having a first input connected to the input data rate signal input and a second input connected to the digital signal input to produce a logical output that gates output from the digital signal output of the adder.

2 . The device of claim 1 , wherein the weight generator includes:

a subtractor having a difference output, a minuend input connected to the difference output, and a subtrahend input:

a ripple counter, connected to the subtrahend input:

a first register, connected to the input data rate signal input and between the difference output and the weight signal output to time gate the subtractor: and

a second register, connected to the ripple counter and the input data rate signal input to time gate the ripple counter.

3 . The device of claim 1 , wherein the weight generator includes:

a subtractor/adder having a difference/sum output, a first input connected to the difference/sum output, a second input, and a subtraction/addition selector input:

a counter, connected to the second input, the data rate signal input, and a second data rate signal input:

a first register, connected to the data rate signal input and between the difference output and the weight signal output to time gate the subtractor/adder; and

a second register, connected to the counter and the second input data rate signal input to time gate output from the counter to the subtractor/adder; and

a cycle signal input connected to an up/down count selector input of the counter and the subtraction/addition selector input to alter whether the counter counts upward or downward and whether the second input is added to the first input or subtracted from the first input of the subtractor/adder based on a predetermined number of clock cycles.

4 . The device of claim 1 , wherein the weight generator includes:

a second subtractor having a second difference output, a second first input connected to the second difference output, a selector input, and a second subtraction selector input:

a counter, connected to the selector input, the data rate signal input, and a second data rate signal input:

a first register, connected to the data rate signal input and between the difference/sum output and the weight signal output to time gate the second subtractor: and

a second register, connected to the counter and the second input data rate signal input to time gate output from the counter to the second subtractor; and

a cycle signal input connected to a down count selector input of the counter and the second subtraction selector input to alter whether the counter counts upward or downward and that the second input is subtracted from the first input of the subtractor based on a predetermined number of clock cycles.

5 . The device of claim 1 , wherein the weight generator includes:

a second adder having a second sum output, a second first input connected to the sum output, a selector input, and an addition selector input:

a counter, connected to the selector input, the data rate signal input, and a second data rate signal input:

a first register, connected to the data rate signal input and between the sum output and the weight signal output to time gate the second adder; and

a second register, connected to the counter and the second input data rate signal input to time gate output from the counter to the second adder; and

a cycle signal input connected to an up/down count selector input of the counter and the addition selector input to alter whether the counter counts upward or downward and that the second input is added to the first input of the second adder based on a predetermined number of clock cycles.

6 . The device of claim 1 , operating according to a filter kernel of:

w

n

=

∑

i

=

1

N

i

-

∑

i

=

1

n

-

1

i

=

N

2

+

N

2

-

n

2

-

n

2

,

where N and n are filter coefficients.

7 . The device of claim 1 , operating according to a filter kernel of:

w

n

=

{

N

2

+

N

2

-

(

N

-

n

+

1

)

2

-

(

N

-

n

+

1

)

2

n

=

1

,

2

,

…

,

N

;

N

2

+

N

2

-

(

n

-

N

+

1

)

2

-

(

n

-

N

+

1

)

2

n

=

N

+

1

,

…

,

2

⁢

N

-

1

;

,

where N and n are filter coefficients.

8 . A linear decimation filter, comprising:

a weight generator, configured to generate a weight signal based on a digital input signal;

an adder, configured to generate a digital output signal based on the weight signal and the digital signal output from an earlier clock cycle; and

an AND-gate, configured to gate output from the adder based on the digital input signal and an input data rate signal.

9 . The filter of claim 8 , wherein the weight generator includes:

a subtractor having a difference output, a minuend input connected to the difference output, and a subtrahend input;

a ripple counter, connected to the subtrahend input;

a first register, configured to time gate the subtractor; and

a second register, configured to time gate the ripple counter based on the input data rate signal.

10 . The filter of claim 8 , wherein the weight generator includes:

a subtractor/adder, configured to produce a selected one of a difference output or a sum output based on an add/subtract selection signal, a first input to the subtractor/adder, and a second input to the subtractor/adder;

a counter, configured to provide the second input to the subtractor/adder based on an count stored in the counter that is affected by an up/down count selector input to count upwards or downwards for a given clock cycle, wherein the up/down count selector input selects which one of the difference output or the sum output that the subtractor/adder produces for the given clock cycle.

11 . The filter of claim 10 , wherein the subtractor/adder operates to produce the sum output when the counter operations to count upwards.

12 . The filter of claim 10 , wherein the subtractor/adder operates to produce the difference output when the counter operations to count downwards.

13 . The filter of claim 8 , operating according to a filter kernel of:

w

n

=

∑

i

=

1

N

i

-

∑

i

=

1

n

-

1

i

=

N

2

+

N

2

-

n

2

-

n

2

,

where N and n are filter coefficients.

14 . The filter of claim 8 , operating according to a filter kernel of:

w

n

=

{

N

2

+

N

2

-

(

N

-

n

+

1

)

2

-

(

N

-

n

+

1

)

2

n

=

1

,

2

,

…

,

N

;

N

2

+

N

2

-

(

n

-

N

+

1

)

2

-

(

n

-

N

+

1

)

2

n

=

N

+

1

,

…

,

2

⁢

N

-

1

;

,

where N and n are filter coefficients.