Digital phase-locked loops
A digital phase-locked loop includes a first clock divider, a decimation filter, a proportional integral filter, a signal conditioner, and a digitally controlled oscillator. The first clock divider divides a first clock signal including a first clock rate to generate a second clock signal including a second clock rate less than the first clock rate. The decimation filter converts an input signal at the first clock rate to an output signal at the second clock rate. The proportional integral filter filters the output signal at the second clock rate to generate a filtered output signal. The signal conditioner conditions the filtered output signal at the second clock rate to generate a conditioned output signal. The digitally controlled oscillator generates a carrier clock signal in response to the conditioned output signal.
1. A digital phase-locked loop comprising:
a first clock divider to divide a first clock signal comprising a first clock rate to generate a second clock signal comprising a second clock rate less than the first clock rate;
a decimation filter to convert an input signal at the first clock rate to an output signal at the second clock rate;
a proportional integral filter to filter the output signal at the second clock rate to generate a filtered output signal;
a signal conditioner to condition the filtered output signal at the second clock rate to generate a conditioned output signal; and
a digitally controlled oscillator to generate a carrier clock signal in response to the conditioned output signal.
2. The digital phase-locked loop of claim 1 , further comprising:
a second clock divider to divide the carrier clock signal to generate a third clock signal comprising a third clock rate greater than the second clock rate;
wherein the signal conditioner comprises:
a first portion to condition the filtered output signal at the second clock rate to generate an intermediate output signal; and
a second portion to condition the intermediate output signal at the third clock rate to generate the conditioned output signal.
3. The digital phase-locked loop of claim 1 , wherein the decimation filter comprises a cascaded integrator comb filter or a polyphase filter.
4. The digital phase-locked loop of claim 1 , further comprising:
a crystal oscillator circuit to generate a reference signal; and
a time to digital converter to compare a phase of the reference signal to a phase of a feedback signal to generate the input signal, the feedback signal based on the carrier clock signal and the input signal proportional to a time error between the reference signal and the feedback signal.
5. The digital phase-locked loop of claim 4 , further comprising:
a buffer to buffer the reference signal to generate the first clock signal.
6. The digital phase-locked loop of claim 1 , further comprising:
a modulator to generate a modulation signal,
wherein the signal conditioner conditions the filtered output signal based on the modulation signal to generate the conditioned output signal.
7. The digital phase-locked loop of claim 1 , wherein the signal conditioner comprises a predistortion and calibration signal conditioner.
8. The digital phase-locked loop of claim 1 , wherein the signal conditioner comprises a delta-sigma modulator.
9. A system comprising:
a controller;
a transceiver communicatively coupled to the controller, the transceiver comprising a digital phase-locked loop; and
at least one antenna electrically coupled to the transceiver,
wherein the digital phase-locked loop comprises:
a first clock divider to divide a first clock signal comprising a first clock rate to generate a second clock signal comprising a second clock rate less than the first clock rate;
a decimation filter to convert an input signal at the first clock rate to an output signal at the second clock rate;
a proportional integral filter to filter the output signal at the second clock rate to generate a filtered output signal;
a signal conditioner to condition the filtered output signal at the second clock rate to generate a conditioned output signal; and
a digitally controlled oscillator to generate a carrier clock signal in response to the conditioned output signal.
10. The system of claim 9 , wherein the digital phase-locked loop further comprises:
a second clock divider to divide the carrier clock signal to generate a third clock signal comprising a third clock rate greater than the second clock rate;
wherein the signal conditioner comprises:
a first portion to condition the filtered output signal at the second clock rate to generate an intermediate output signal; and
a second portion to condition the intermediate output signal at the third clock rate to generate the conditioned output signal.
11. The system of claim 9 , further comprising:
a modulator to generate a modulation signal,
wherein the signal conditioner conditions the filtered output signal based on the modulation signal to generate the conditioned output signal.
12. The system of claim 9 , wherein the transceiver comprises a radar transceiver, a Wi-Fi transceiver, or a Bluetooth transceiver.
13. The system of claim 9 , wherein the digital phase-locked loop comprises a feedback divider digital phase-locked loop, a phase domain digital phase-locked loop, or a sub-sampling digital phase-locked loop.
14. A method comprising:
dividing a first clock signal comprising a first clock rate to generate a second clock signal comprising a second clock rate less than the first clock rate;
converting, via a decimation filter, an input signal at the first clock rate to an output signal at the second clock rate;
filtering, via a proportional integral filter, the output signal at the second clock rate to generate a filtered output signal;
conditioning the filtered output signal at the second clock rate to generate a conditioned output signal; and
generating, via a digitally controlled oscillator, a carrier clock signal in response to the conditioned output signal.
15. The method of claim 14 , further comprising:
dividing the carrier clock signal to generate a third clock signal comprising a third clock rate greater than the second clock rate;
wherein conditioning the filtered output signal comprises:
conditioning the filtered output signal at the second clock rate to generate an intermediate output signal; and
further conditioning the intermediate output signal at the third clock rate to the generate the conditioned output signal.
16. The method of claim 14 , further comprising:
generating, via a crystal oscillator circuit, a reference signal; and
comparing a phase of the reference signal to a phase of a feedback signal to generate the input signal, the feedback signal based on the carrier clock signal and the input signal proportional to a time error between the reference signal and the feedback signal.
17. The method of claim 16 , further comprising:
buffering the reference signal to generate the first clock signal.
18. The method of claim 16 , further comprising:
generating, within a radio transceiver, a phase modulation signal;
wherein conditioning the filtered output signal comprises conditioning the filtered output signal based on the phase modulation signal to generate the conditioned output signal.
19. The method of claim 18 , further comprising:
generating, within the radio transceiver, a radio frequency clock signal in response to the carrier clock signal.
20. The method of claim 19 , further comprising:
generating, within the radio transceiver, an amplitude modulation signal; and
generating, via a radio frequency digital to analog converter clocked by the radio frequency clock signal, a radio frequency output signal in response to the amplitude modulation signal.