Self-contained and configurable debugging mechanism for stream-based hardware accelerators
A hardware accelerator includes a plurality of functional circuits, a stream switch, a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.
1 . A hardware accelerator, comprising:
a plurality of functional circuits;
a stream switch;
a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits; and
a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors, via wired probes, a set of data signals for interrupts from the hardware accelerator to one or more host processors and a set of data signals between the stream switch and at least one of (a) one or more of the functional circuits or (b) one or more of the DMA channels, and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.
2 . The hardware accelerator of claim 1 , wherein the debug and trace unit does not require at least one of dedicated memories, dedicated buses, or dedicated debugging interfaces.
3 . The hardware accelerator of claim 2 , wherein the debug and trace unit shares a bus with the plurality of functional circuits.
4 . The hardware accelerator of claim 3 , wherein access to the debug and trace unit has a lowest priority on the shared bus to avoid interfering with system behavior of the hardware accelerator.
5 . The hardware accelerator of claim 1 , wherein a quantity of at least one of the one or more event counters, one or more triggers, or one or more tracers is subject to configuration.
6 . The hardware accelerator of claim 5 , wherein the configuration is performed based on one or more configuration registers of the hardware accelerator.
7 . The hardware accelerator of claim 1 , wherein the trace data packets are output via the stream switch to at least one of the DMA channels.
8 . The hardware accelerator of claim 1 , wherein the trace data packets are output via the stream switch to at least a local buffer of the hardware accelerator.
9 . The hardware accelerator of claim 8 , wherein the local buffer is coupled to at least one of the DMA channels via the stream switch.
10 . A system, comprising:
a host device; and
a hardware accelerator, the hardware accelerator including:
a plurality of functional circuits;
a stream switch;
a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits; and
a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors, via wired probes, a set of data signals between the stream switch and one or more internal buffers of the hardware accelerator and a set of data signals between the stream switch and at least one of (a) one or more of the functional circuits or (b) one or more of the DMA channels, and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.
11 . The system of claim 10 , wherein the debug and trace unit does not require at least one of dedicated memories, dedicated buses, or dedicated debugging interfaces.
12 . The system of claim 11 , wherein the debug and trace unit shares a bus with the plurality of functional circuits.
13 . The system of claim 12 , wherein access to the debug and trace unit has a lowest priority on the shared bus to avoid interfering with system behavior of the hardware accelerator.
14 . The system of claim 10 , wherein a quantity of at least one of the one or more event counters, one or more triggers, or one or more tracers is subject to configuration.
15 . The system of claim 14 , wherein the configuration is performed based on one or more configuration registers of the hardware accelerator.
16 . The system of claim 10 , wherein the trace data packets are output via the stream switch to at least one of the DMA channels.
17 . The system of claim 10 , wherein the trace data packets are output via the stream switch to at least a local buffer of the hardware accelerator.
18 . The system of claim 17 , wherein the local buffer is coupled to at least one of the DMA channels via the stream switch.
19 . A method, comprising:
streaming data between a plurality of direct memory access (DMA) channels of a hardware accelerator and a plurality of functional circuits of the hardware accelerator via a stream switch;
implementing debug and trace functions within the hardware accelerator based on configurations obtained via configuration registers;
monitoring, via wired probes, data signals between one or more of the DMA channels and memories external to the hardware accelerator and data signals between the stream switch and at least one of (a) one or more of the functional circuits or (b) one or more of the DMA channels; and
outputting trace data via the stream switch.
20 . The method of claim 19 , wherein implementing the debug and trace functions within the hardware accelerator does not require at least one of dedicated memories, dedicated buses, or dedicated debugging interfaces.
21 . The method of claim 20 , wherein implementing the debug and trace functions comprises sharing a bus with the plurality of functional circuits.
22 . The method of claim 21 , wherein access to the debug and trace functions has a lowest priority on the shared bus to avoid interfering with system behavior of the hardware accelerator.
23 . The method of claim 19 , wherein the configuration registers include configuration information to configure at least one of one or more event counters, one or more triggers, or one or more tracers corresponding to the debug and trace functions.
24 . The method of claim 19 , wherein the trace data is output via the stream switch to at least one of the DMA channels.
25 . The method of claim 19 , wherein the trace data is output via the stream switch to at least a local buffer of the hardware accelerator.
26 . The method of claim 25 , wherein the local buffer is further used to output the trace data to at least one of the DMA channels via the stream switch.
27 . A non-transitory computer-readable medium having contents which cause a system including one or more processors to perform actions comprising:
streaming data between a plurality of direct memory access (DMA) channels of a hardware accelerator and a plurality of functional circuits of the hardware accelerator via a stream switch;
implementing debug and trace functions within the hardware accelerator based on configurations obtained via configuration registers;
monitoring, via wired probes without requiring dedicated buses, data signals between the stream switch and at least one of (a) one or more of the functional circuits or (b) one or more of the DMA channels; and
outputting trace data via the stream switch.
28 . The non-transitory computer-readable medium of claim 27 , wherein implementing the debug and trace functions within the hardware accelerator does not require at least one of dedicated memories, dedicated buses, or dedicated debugging interfaces.
29 . The non-transitory computer-readable medium of claim 28 , wherein implementing the debug and trace functions comprises sharing a bus with the plurality of functional circuits.
30 . The non-transitory computer-readable medium of claim 29 , wherein access to the debug and trace functions has a lowest priority on the shared bus to avoid interfering with system behavior of the hardware accelerator.
31 . The non-transitory computer-readable medium of claim 27 , wherein the configuration registers include configuration information to configure at least one of one or more event counters, one or more triggers, or one or more tracers corresponding to the debug and trace functions.
32 . The non-transitory computer-readable medium of claim 27 , wherein the trace data is output via the stream switch to at least one of the DMA channels.
33 . The non-transitory computer-readable medium of claim 27 , wherein the trace data is output via the stream switch to at least a local buffer of the hardware accelerator.
34 . The non-transitory computer-readable medium of claim 33 , wherein the local buffer is further used to output the trace data to at least one of the DMA channels via the stream switch.