CUSTOM COMPUTE CORES IN INTEGRATED CIRCUIT DEVICES
A system includes a processor and a hardware accelerator coupled to the processor. The hardware accelerator includes data analysis elements configured to analyze a data stream based on configuration data and to output a result, and an integrated circuit device that includes a DMA engine that writes input data to and read output data from the data analysis elements, one or more preprocessing cores that receive the input data from the DMA engine prior to the DMA engine writing the input data to the one or more data analysis elements and perform custom preprocessing functions on the input data, and one or more post-processing cores that receive the output data from the DMA engine after the output data is read from the data analysis elements but prior to the output data being output to the processor and perform custom post-processing functions on the output data.
1 . A device, comprising:
a first interface circuit that when in operation receives data;
one or more preprocessing cores that when in operation generate formatted data based upon the data received at the first interface circuit; and
a second interface circuit, wherein the second interface circuit when in operation receives the formatted data and transmits the formatted data.
2 . The device of claim 1 , wherein the one or more preprocessing cores when in operation generate the formatted data by compressing, organizing, sorting, merging, deleting, modifying, inserting, segmenting, or filtering the data received at the first interface circuit.
3 . The device of claim 1 , wherein the one or more preprocessing cores are implemented using a software development kit.
4 . The device of claim 1 , wherein the one or more preprocessing cores when in operation generate the formatted data into a format compatible with a second device that when in operation receives the formatted data from the second interface circuit.
5 . The device of claim 4 , wherein the second interface circuit when in operation receives second data.
6 . The device of claim 5 , comprising one or more post-processing cores that when in operation generate second formatted data based upon the second data received at the second interface circuit.
7 . The device of claim 6 , wherein the first interface circuit when in operation receives the second formatted data and transmits the second formatted data.
8 . The device of claim 7 , wherein the one or more post-processing cores when in operation generate the second formatted data into a format compatible with a second device that when in operation receives the formatted data from the first interface circuit.
9 . The device of claim 6 , wherein the one or more post-processing cores when in operation generate the second formatted data by compressing, organizing, sorting, merging, deleting, modifying, inserting, segmenting, or filtering the second data received at the second interface circuit.
10 . The device of claim 6 , wherein the one or more post-processing cores are implemented using a software development kit.
11 . The device of claim 1 , wherein the first interface circuit comprises a transceiver that receives and transmits signals according to a first protocol, wherein the second interface circuit comprises a second transceiver that receives and transmits second signals according to a second protocol that differs from the first protocol.
12 . A device, comprising:
a first interface circuit that when in operation receives data;
a direct memory access (DMA) engine coupled to the first interface circuit, wherein the DMA engine when in operation coordinates transmission of the data received by the first interface circuit;
one or more preprocessing cores that when in operation generate formatted data based upon the data received at the first interface; and
a second interface circuit, wherein the second interface circuit when in operation receives the formatted data and transmits the formatted data.
13 . The device of claim 12 , wherein the DMA engine when in operation receives the formatted data from the one or more preprocessing cores and transmits the formatted data to the second interface circuit.
14 . The device of claim 12 , wherein the second interface circuit when in operation receives second data.
15 . The device of claim 14 , comprising one or more post-processing cores that when in operation generate second formatted data based upon the second data received at the second interface circuit.
16 . The device of claim 15 , wherein the first interface circuit when in operation receives the second formatted data and transmits the second formatted data.
17 . The device of claim 16 , wherein the DMA engine when in operation receives the second formatted data from the one or more post-processing cores and transmits the second formatted data to the first interface circuit.
18 . A method, comprising:
receiving first data at a first interface of an integrated device;
performing one or more preprocessing functions on the first data to generate preprocessed data using one or more preprocessing cores of the integrated device; and
transmitting the preprocessed data from a second interface of the integrated device to a second device.
19 . The method of claim 18 , comprising:
receiving second data at the second interface of the integrated device from the second device;
performing one or more post-processing functions on the second data to generate post-processed data using one or more post-processing cores of the integrated device; and
transmitting the post-processed data from the first interface of the integrated device.
20 . The method of claim 19 , comprising:
providing the first data received by the first interface to the one or more preprocessing cores of the integrated device via a direct memory access (DMA) engine;
providing the preprocessed data to the second interface via the DMA engine;
providing the second data received by the second interface to the one or more post-processing cores of the integrated device via the DMA engine; and
providing the post-processed data to the second interface via the DMA engine.