Storing data objects in a storage network with multiple memory types
A processing system of a storage network operates by: selecting a queue memory type of a plurality of memory types to store a data object, based on a size parameter associated with the data object; storing the data object in a queue memory device having the queue memory type, when the queue memory type is selected; selecting a main memory type of a plurality of memory types to store the data object, when the queue memory type is not selected; and storing the data object in a main memory device having the main memory type, when the queue memory type is not selected; wherein the data object is dispersed error encoded and stored as a plurality of encoded data slices.
1. A method for execution by a processing system that includes a processing circuit, the method comprises:
selecting a queue memory type of a plurality of memory types to store a data object, based on a size parameter associated with the data object;
storing the data object in a queue memory device having the queue memory type, when the queue memory type is selected;
selecting a main memory type of a plurality of memory types to store the data object, when the queue memory type is not selected; and
storing the data object in a main memory device having the main memory type, when the queue memory type is not selected;
wherein the data object is dispersed error encoded and stored as a plurality of encoded data slices.
2. The method of claim 1 , wherein the size parameter indicates a size associated with the data object.
3. The method of claim 1 , wherein the size parameter indicates temporary storage of the data object.
4. The method of claim 1 , wherein the plurality of memory types include a first memory type and a second memory type and wherein the first memory type has a lower latency compared with the second memory type.
5. The method of claim 1 , wherein the plurality of memory types include a first memory type and a second memory type and wherein the first memory type has a lower cost compared with the second memory type.
6. The method of claim 1 , wherein the queue memory device is implemented via a solid state memory device, and wherein the queue memory device has a lower latency compared to other memory devices associated with at least one other memory type.
7. The method of claim 1 , wherein the queue memory device is implemented via a solid state memory device, and wherein the queue memory device has a higher cost compared to other memory devices associated with at least one other memory type.
8. The method of claim 1 , wherein at least one other memory type of the plurality of memory types includes a main memory type.
9. The method of claim 8 , wherein other memory devices associated with the main memory type are implemented via random access memory devices.
10. The method of claim 9 , wherein the random access devices have a lower cost compared with the queue memory device.
11. A processing system of a storage network comprises:
at least one processor;
a memory that stores operational instructions, that when executed by the at least one processor cause the processing system to operations including:
selecting a queue memory type of a plurality of memory types to store a data object, based on a size parameter associated with the data object;
storing the data object in a queue memory device having the queue memory type, when the queue memory type is selected;
selecting a main memory type of a plurality of memory types to store the data object, when the queue memory type is not selected; and
storing the data object in a main memory device having the main memory type, when the queue memory type is not selected;
wherein the data object is dispersed error encoded and stored as a plurality of encoded data slices.
12. The processing system of claim 11 , the size parameter indicates a size associated with the data object.
13. The processing system of claim 11 , wherein the size parameter indicates temporary storage of the data object.
14. The processing system of claim 11 , wherein the plurality of memory types include a first memory type and a second memory type and wherein the first memory type has a lower latency compared with the second memory type.
15. The processing system of claim 11 , wherein the plurality of memory types include a first memory type and a second memory type and wherein the first memory type has a lower cost compared with the second memory type.
16. The processing system of claim 11 , wherein the queue memory device is implemented via a solid state memory device, and wherein the queue memory device has a lower latency compared to other memory devices associated with at least one other memory type.
17. The processing system of claim 11 , wherein the queue memory device is implemented via a solid state memory device, and wherein the queue memory device has a higher cost compared to other memory devices associated with at least one other memory type.
18. The processing system of claim 11 , wherein at least one other memory type of the plurality of memory types includes a main memory type.
19. The processing system of claim 18 , wherein other memory devices associated with the main memory type are implemented via random access memory devices.
20. The processing system of claim 19 , wherein the random access devices have a lower cost compared with the queue memory device.