HEMT TRANSISTOR
The present disclosure relates to a HEMT transistor comprising a first semiconductor layer, a gate arranged on a first surface of the first semiconductor layer, a first passivation layer made of a first material on the sides of the gate, the first passivation layer further extending over a first portion of said surface of the first semiconductor layer, and a second passivation layer made of a second material different from the first material on a second portion of said surface of the first semiconductor layer next to the first passivation layer.
1 . A HEMT transistor comprising:
a first semiconductor layer;
a gate arranged on a first surface of the first semiconductor layer;
a first passivation layer made of a first material on two or more sides of the gate, the first passivation layer further extending over a first portion of said first surface of the first semiconductor layer; and
a second passivation layer made of a second material different from the first material on a second portion of said first surface of the first semiconductor layer next to the first passivation layer.
2 . The HEMT transistor according to claim 1 , wherein the first semiconductor layer is based on gallium nitride.
3 . The HEMT transistor according to claim 2 , wherein the first semiconductor layer is made of aluminum-gallium nitride.
4 . The HEMT transistor according to claim 1 , wherein the first passivation layer is made of alumina.
5 . The HEMT transistor according to claim 1 , wherein the second passivation layer is made of aluminum nitride.
6 . The HEMT transistor according to claim 1 , comprising a second semiconductor layer in contact with a second surface of the first semiconductor layer, opposite to the first surface.
7 . The HEMT transistor according to claim 6 , wherein the second semiconductor layer is made of gallium nitride.
8 . The HEMT transistor according to claim 1 , comprising a source contact metallization and a drain contact metallization, respectively arranged on either side of the gate.
9 . The HEMT transistor according to claim 8 , wherein the first passivation layer extends laterally from the gate towards the drain contact metallization, over a portion only of the first surface between the gate and the drain contact metallization.
10 . The HEMT transistor according to claim 8 , wherein the first passivation layer extends laterally from the gate to the source contact metallization.
11 . The HEMT transistor according to claim 8 , wherein the second passivation layer extends laterally from an edge of the first passivation layer located between the gate and the drain contact metallization, to the drain contact metallization.
12 . The HEMT transistor according to claim 1 , wherein the first passivation layer is covered with an insulating layer.
13 . The HEMT transistor according to claim 12 , wherein the second passivation layer covers the side of the insulating layer located between the gate and a drain contact metallization and extends over a portion of the insulating layer towards the gate.
14 . Method of forming an HEMT transistor comprising the following successive steps:
a) forming a first semiconductor layer;
b) forming a gate on a first surface of the first semiconductor layer;
c) forming a first passivation layer made of a first material on two or more sides of the gate, the first passivation layer further extending over a first portion of said first surface of the first semiconductor layer; and
d) forming a second passivation layer made of a second material different from the first material on a second portion of said first surface of the first semiconductor layer next to the first passivation layer.