MULTIPLE PIXEL BINNING WITH GLOBAL SHUTTER OPERATION
Structures are disclosed for a binned set of pixels (such as a 2×2 set of pixels) of a pixel array that shares a same readout circuit and can operate with a global shutter. The global shutter allows for greater charge storage from each pixel and for the charge from each of the binned pixels to be collected simultaneously. In an example, each of the binned pixels includes a photodetector, a transfer gate, and a storage gate. The storage gate of each binned pixel may be linked as part of a global shutter. The readout circuit can be coupled to the transfer gate of each of the binned pixels and includes its own second transfer gate that separates the pixels from a storage or sensing node. The photodetector signal on the sensing node can be amplified via a source follower component and ultimately read out to a column amplifier.
1 . An image sensor, comprising:
at least two pixels with each pixel of the at least two pixels including a photodetector, a storage gate coupled to the photodetector, and a first transfer gate coupled to the storage gate;
a second transfer gate having an input coupled to an output of each first transfer gate of each of the at least two pixels; and
a control field effect transistor (FET), wherein a gate of the control FET is configured to receive charge from an output of the second transfer gate.
2 . The image sensor of claim 1 , wherein the first transfer gate of each of the at least two pixels is a FET and the storage gate of each of the at least two pixels is a FET.
3 . The image sensor of claim 2 , wherein a length of the storage gate FET of each of the at least two pixels is higher than a length of the transfer gate FET of each of the at least two pixels.
4 . The image sensor of claim 2 , wherein the storage gate of each of the at least two pixels has a first terminal coupled to the corresponding photodetector and a second terminal coupled to the corresponding first transfer gate, the first terminal having a higher threshold voltage compared to the second terminal.
5 . The image sensor of claim 4 , wherein the second terminal has a negative threshold voltage.
6 . The image sensor of claim 1 , wherein the at least two pixels comprises four pixels arranged in a 2×2 grid.
7 . An imaging system comprising the image sensor of claim 1 .
8 . An image sensor, comprising:
a pixel array having at least one column of addressable pixels, wherein the at least one column of addressable pixels includes at least two pixels with each pixel of the at least two pixels including a photodetector, a storage gate coupled to the photodetector, and a first transfer gate coupled to the storage gate;
a readout circuit including
a second transfer gate having an input coupled to an output of each first transfer gate of each of the at least two pixels, and
a control field effect transistor (FET), wherein a gate of the control FET is configured to receive charge from an output of the second transfer gate.
9 . The image sensor of claim 8 , wherein the first transfer gate of each of the at least two pixels is a FET and the storage gate of each of the at least two pixels is a FET.
10 . The image sensor of claim 9 , wherein the length of the storage gate FET of each of the at least two pixels is at least 10 times higher than the length of the transfer gate FET of each of the at least two pixels.
11 . The image sensor of claim 9 , wherein the storage gate of each of the at least two pixels has a first terminal coupled to the corresponding photodetector and a second terminal coupled to the corresponding first transfer gate, the first terminal having a higher threshold voltage compared to the second terminal.
12 . The image sensor of claim 11 , wherein the second terminal has a negative threshold voltage.
13 . The image sensor of claim 8 , further comprising a reset switch coupled to the output of the second transfer gate.
14 . A CMOS image sensor (CIS), comprising:
four pixels with each pixel of the four pixels including a photodetector, a storage gate coupled to the photodetector, and a first transfer gate coupled to the storage gate;
a second transfer gate having a single input coupled to an output of each first transfer gate of each of the four pixels; and
a control field effect transistor (FET), wherein a gate of the control FET is configured to receive charge from an output of the second transfer gate.
15 . The CIS of claim 14 , wherein the first transfer gate of each of the four pixels is a FET and the storage gate of each of the four pixels is a FET.
16 . The CIS of claim 15 , wherein a length of the storage gate FET of each of the four pixels is higher than a length of the transfer gate FET of each of the four pixels.
17 . The CIS of claim 16 , wherein the length of the storage gate FET of each of the four pixels is at least 10 times higher than the length of the transfer gate FET of each of the four pixels.
18 . The CIS of claim 15 , wherein the storage gate of each of the four pixels has a first terminal coupled to the corresponding photodetector and a second terminal coupled to the corresponding first transfer gate, the first terminal having a higher threshold voltage compared to the second terminal.
19 . The CIS of claim 18 , wherein the second terminal has a negative threshold voltage.
20 . The CIS of claim 14 , wherein the four pixels are arranged in a 2×2 grid.