Fractional frequency synthesizer utilizing multi-phase divider circuitry
A fractional frequency synthesizer, a fractional PLL, and a method for generating a fractional frequency signal based on a reference signal are provided. An example fractional frequency synthesizer includes a multi-phase clock generator configured to generate a clock vector comprising a plurality of clock signals, each oscillating according to a fractional frequency in relation to the reference frequency and each clock signal offset by a phase offset. The fractional frequency synthesizer includes multi-phase divider circuitry configured to select a clock signal from the clock vector to generate a fractional frequency feedback signal. An accumulator configured to increment a count and a rollover detector configured to determine a rollover value associated with a rollover event on the accumulator are further included. A clock signal is selected based on the rollover value and the fractional frequency feedback signal is generated based at least in part on the selected clock signal.
1 . A fractional frequency synthesizer, comprising:
a multi-phase clock generator configured to generate a clock vector based on a reference signal having a reference frequency,
wherein the clock vector comprises a plurality of clock signals each clock signal oscillating according to a fractional frequency in relation to the reference frequency, and wherein each clock signal is offset by a phase offset; and
multi-phase divider circuitry electrically connected to the multi-phase clock generator and configured to receive the clock vector and select a selected clock signal from the plurality of clock signals to generate a fractional frequency feedback signal, the multi-phase divider circuitry comprising:
an accumulator configured to increment a count according to the fractional frequency; and
a rollover detector configured to determine a rollover value associated with a rollover event of the count on the accumulator;
wherein the selected clock signal is selected based on the rollover value, and
wherein the fractional frequency feedback signal is generated based at least in part on the selected clock signal.
2 . The fractional frequency synthesizer of claim 1 , wherein the multi-phase clock generator comprises a voltage-controlled ring oscillator.
3 . The fractional frequency synthesizer of claim 2 , wherein the voltage-controlled ring oscillator comprises:
a delay line comprising a plurality of delay elements,
wherein the plurality of clock signals comprising the clock vector are transmitted from a plurality of contact points along the delay line.
4 . The fractional frequency synthesizer of claim 1 , wherein the accumulator comprises:
a counter comprising a counter bit quantity number of bits,
wherein the counter is configured to increment the count by a step value.
5 . The fractional frequency synthesizer of claim 4 , wherein the fractional frequency of the plurality of clock signals is determined based at least in part on the counter bit quantity and the step value.
6 . The fractional frequency synthesizer of claim 4 , wherein the rollover value represents the count after the rollover event of the accumulator.
7 . The fractional frequency synthesizer of claim 6 , wherein the selected clock signal is determined based at least in part on a comparison of the rollover value to the step value.
8 . The fractional frequency synthesizer of claim 7 , wherein the comparison of the rollover value to the step value is determined using a division look-up table.
9 . The fractional frequency synthesizer of claim 7 , wherein a frequency offset is determined between a clock edge of the selected clock signal and an ideal clock edge of the fractional frequency feedback signal, and wherein a second selected clock signal corresponding with a next accumulator rollover event is determined based at least in part on the frequency offset.
10 . The fractional frequency synthesizer of claim 1 , wherein the selected clock signal is determined before the rollover event of the accumulator.
11 . The fractional frequency synthesizer of claim 1 , wherein the phase offset between each subsequent clock signal comprising the plurality of clock signals of the clock vector are equal.
12 . The fractional frequency synthesizer of claim 1 , wherein the clock vector comprises at least four clock signals.
13 . A method for generating a fractional frequency feedback signal, comprising:
receiving, from a multi-phase clock generator at multi-phase divider circuitry, a clock vector comprising a plurality of clock signals each clock signal oscillating according to a fractional frequency based at least in part on a reference frequency of a reference signal, and each clock signal offset by a phase offset;
detecting, at the multi-phase divider circuitry, a rollover event of an accumulator configured to increment a count according to the fractional frequency;
determining a rollover value corresponding to the count at the rollover event;
selecting a selected clock signal from the plurality of clock signals based on the rollover value; and
generating the fractional frequency feedback signal based at least in part on the selected clock signal.
14 . The method of claim 13 , wherein the accumulator comprises:
a counter comprising a counter bit quantity number of bits,
wherein the counter is configured to increment the count by a step value based at least in part on the reference frequency.
15 . The method of claim 14 , wherein the fractional frequency of the plurality of clock signals is determined based at least in part on the counter bit quantity and the step value.
16 . The method of claim 14 , wherein the rollover value represents the count after the rollover event of the accumulator.
17 . The method of claim 14 , further comprising:
determining a relation between the rollover value and the step value; and
selecting the selected clock signal based at least in part on the relation.
18 . The method of claim 13 , further comprising:
determining a phase difference between a clock edge of the selected clock signal and an ideal clock edge of the reference signal; and
determining a second selected clock signal corresponding with a next accumulator rollover event based at least in part on the phase difference.
19 . The method of claim 13 , wherein the phase offset between each subsequent clock signal comprising the plurality of clock signals of the clock vector are equal.
20 . A fractional phase-locked loop comprising:
a phase detector module configured to generate a difference signal corresponding to a difference between a phase of a reference signal and a fractional frequency feedback signal;
a loop filter configured to generate a filtered difference signal based at least in part on the difference signal; and
a fractional frequency synthesizer configured to generate the fractional frequency feedback signal, the fractional frequency synthesizer comprising:
a multi-phase clock generator configured to generate a clock vector based on the filtered difference signal, the clock vector comprising a plurality of clock signals each clock signal oscillating according to a fractional frequency based at least in part on a reference frequency of the reference signal, and each clock signal offset by a phase offset; and
multi-phase divider circuitry electrically connected to the multi-phase clock generator and configured to receive the clock vector and select a selected clock signal from the clock vector, to generate the fractional frequency feedback signal, the multi-phase divider circuitry comprising:
an accumulator configured to increment a count according to the fractional frequency; and
a rollover detector configured to detect a rollover value associated with a rollover event of the accumulator;
wherein the selected clock signal is selected based on the rollover value, and
wherein the fractional frequency feedback signal is generated based at least in part on the selected clock signal.