METHOD FOR MANUFACTURING SEVERAL INTEGRATED CIRCUIT PACKAGES
An integrated circuit package includes a support substrate having a mounting face and a lateral wall having an inner face and an outer face. The inner face delimits with the mounting face a cavity. The outer face includes a step extending outwardly of the package. An electronic chip disposed in the cavity and electrically connected to electrically-conductive contact pads. A sealing structure is bonded by a glue to an upper face of the lateral wall to seal the cavity. The glue does not spill out over the outer face of the lateral wall. Electrically-conductive connection elements are located over a lower face of the support substrate and electrically cooperate with the contact pads through an interconnection network located in the support substrate.
1 . A method for manufacturing integrated circuit packages, comprising:
providing a support substrate having a mounting face and comprising a wall projecting over the mounting face, said wall delimiting with the mounting face an array of cavities, the mounting face at each cavity including electrically-conductive contact pads, the support substrate including under each cavity an interconnection network between the electrically-conductive contact pads and a lower face of the support substrate;
forming first trenches extending partially through a thickness of the wall around each cavity;
mounting an electronic integrated circuit chip on the mounting face of the support substrate respectively in each cavity and electrically cooperating with corresponding electrically-conductive contact pads;
sealing each cavity by gluing a respective sealing structure over an upper face of the wall using an adhesive configured to spill out into the first trenches, so as to obtain an array of packages;
forming electrically-conductive connection elements under each cavity electrically cooperating with the corresponding interconnection network; and
individualizing the array of packages by cutting said wall and the support substrate to form, in said wall and in the support substrate, second trenches that are thinner than the first trenches and which extend the first trenches through to the lower face of the support substrate.
2 . The method according to claim 1 , wherein a contact angle of the adhesive over the upper face of the wall is larger than 30°.
3 . The method according to claim 1 , wherein the first trenches have a first width, the second trenches have a second width and a difference between the first width and the second width is larger than or equal to 100 μm.
4 . The method according to claim 1 , wherein a depth of the first trenches is between 50% and 80% of the thickness of the wall.
5 . An integrated circuit package, including:
a support substrate having a mounting face;
a lateral wall disposed over the mounting face, having an inner face and an outer face, the inner face delimiting with the mounting face a cavity, the outer face including a step extending outwardly of the package;
an electronic integrated circuit chip disposed in the cavity above the mounting face of the support substrate and electrically connected to electrically-conductive contact pads located at the mounting face;
a sealing structure, bonded by an adhesive, over an upper face of the lateral wall and sealing the cavity, said adhesive not spilling out over the outer face of the lateral wall; and
electrically-conductive connection elements located over a lower face of the support substrate and electrically cooperating with said electrically-conductive contact pads through an interconnection network located in the support substrate.
6 . The package according to claim 5 , wherein a contact angle of the adhesive over the upper face of the lateral wall is larger than 30°.
7 . The package according to claim 5 , wherein the step is located at a distance from the upper face of the lateral wall and has a width larger than or equal to 100 μm.
8 . The package according to claim 7 , wherein the distance is comprised between 50% and 80% of a height of the lateral wall.