Delay control circuit, delay control method and memory
A delay control circuit includes a delay circuit. The delay circuit is configured to receive an initial command signal, and to perform a non-clock-triggered delay processing on the initial command signal to obtain a target command signal. The initial command signal is generated based on an ECS operation mode, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation and the target command signal is used for performing a second operation.
1 . A delay control circuit, comprising:
a delay circuit, configured to receive an initial command signal, and to perform a non-clock-triggered delay processing on the initial command signal to obtain a target command signal, wherein the initial command signal is generated based on an Error Check and Scrub (ECS) operation mode, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation, and the target command signal is used for performing a second operation;
wherein the delay circuit comprises a delay line, and the delay line comprises at least one delay sub-circuit, and
a power supply terminal of each of the at least one delay sub-circuit is configured to receive a first voltage.
2 . The delay control circuit of claim 1 , further comprising a voltage generation circuit, wherein
the voltage generation circuit is configured to generate the first voltage which is stable.
3 . The delay control circuit of claim 2 , wherein the voltage generation circuit comprises a reference voltage circuit and a voltage regulator circuit, and
the reference voltage circuit is configured to receive an initial voltage and generate a reference voltage based on the initial voltage; and
the voltage regulator circuit is configured to perform a voltage regulator processing on the reference voltage to generate the first voltage which is stable.
4 . The delay control circuit of claim 2 , further comprising a voltage conversion circuit, wherein
the voltage conversion circuit is configured to perform a voltage conversion processing on the target command signal, to convert an operating voltage of the target command signal from the first voltage to a second voltage.
5 . The delay control circuit of claim 4 , wherein the first voltage is a delay circuit voltage VDLY and the second voltage is an operating voltage VDD.
6 . The delay control circuit of claim 2 , wherein a number of the at least one delay sub-circuit is N, and the N is an integer greater than 0, and
in case that the N is equal to 1, an input terminal of the delay sub-circuit is configured to receive the initial command signal, and an output terminal of the delay sub-circuit is configured to output the target command signal; and
in case that the N is greater than 1, an input terminal of a first delay sub-circuit is configured to receive the initial command signal, an input terminal of an i-th delay sub-circuit is connected to an output terminal of an (i−1)-th delay sub-circuit, and an output terminal of an N-th delay sub-circuit is configured to output the target command signal, wherein the i is an integer greater than 1 and less than or equal to the N.
7 . The delay control circuit of claim 6 , wherein the delay sub-circuit comprises M inverters, and a power supply terminal of each of the M inverters is connected to the voltage generation circuit, and the M is an integer greater than 0, and
in case that the M is equal to 1, an input terminal of the inverter is configured to receive an input signal of the delay sub-circuit, and an output terminal of the inverter is configured to output an output signal of the delay sub-circuit; and
in case that the M is greater than 1, an input terminal of a first inverter is configured to receive the input signal of the delay sub-circuit, an input terminal of a j-th inverter is connected to an output terminal of a (j−1)-th inverter, and an output terminal of an M-th inverter is configured to output the output signal of the delay sub-circuit, wherein the j is an integer greater than 1 and less than or equal to the M.
8 . The delay control circuit of claim 6 , wherein the i-th delay sub-circuit comprises an inverter and L load capacitors, and the L is an integer greater than 0, wherein
an input terminal of the inverter is configured to receive an input signal; and
an output terminal of the inverter is connected to the L load capacitors, a power supply terminal of each of the L load capacitors is connected to the voltage generation circuit, and a grounding terminal of each of the L load capacitors is connected to ground, and
wherein in case that the i is equal to 1, the input signal is the initial command signal; and in case that the i is greater than 1 and less than or equal to the N, the input signal is an output signal of the (i−1)-th delay sub-circuit.
9 . The delay control circuit of claim 1 , wherein the delay sub-circuit is configured to delay the received input signal for a first duration and output the delayed signal; and
wherein a product value of a number of the at least one delay sub-circuit and the first duration is equal to the time interval between the target command signal and the initial command signal.
10 . The delay control circuit of claim 1 , further comprising a buffer, wherein
the buffer is configured to receive an ECS command signal and generate the initial command signal based on the ECS command signal.
11 . The delay control circuit of claim 10 , further comprising an ECS control circuit, wherein
the ECS control circuit is configured to generate the ECS command signal based on a self-refresh signal in the ECS operation mode.
12 . The delay control circuit of claim 1 , wherein the initial command signal comprises an activate signal, and the target command signal comprises a read signal, or
the initial command signal comprises a read signal, and the target command signal comprises a write signal, or
the initial command signal comprises a write signal, and the target command signal comprises a precharge signal,
wherein the activate signal is used for performing an activate operation, the read signal is used for performing a read operation, the write signal is used for performing a write operation, and the precharge signal is used for performing a precharge operation.
13 . A delay control circuit, comprising:
a delay circuit, configured to receive an initial command signal, and to perform a non-clock-triggered delay processing on the initial command signal to obtain a target command signal, wherein a power supply terminal of the delay circuit is configured to receive a first voltage which is stable, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation, and the target command signal is used for performing a second operation; and
a voltage generation circuit, configured to generate the first voltage which is stable.
14 . The delay control circuit of claim 13 , wherein the voltage generation circuit comprises a reference voltage circuit and a voltage regulator circuit, and
the reference voltage circuit is configured to receive an initial voltage and generate a reference voltage based on the initial voltage; and
the voltage regulator circuit is configured to perform a voltage regulator processing on the reference voltage to generate the first voltage which is stable.
15 . The delay control circuit of claim 13 , further comprising a voltage conversion circuit, wherein
the voltage conversion circuit is configured to perform a voltage conversion processing on the target command signal, to covert an operating voltage of the target command signal from the first voltage to a second voltage.
16 . A delay control method, comprising:
receiving an initial command signal; and
performing a non-clock-triggered delay processing on the initial command signal to obtain a target command signal, wherein the initial command signal is generated based on an Error Check and Scrub (ECS) operation mode, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation, and the target command signal is used for performing a second operation;
wherein a power supply terminal of the delay circuit is used for receiving a first voltage which is stable, and the first voltage is generated by a voltage generation circuit.
17 . A delay control circuit, comprising:
a delay circuit, configured to receive an initial command signal, and to perform a non-clock-triggered delay processing on the initial command signal to obtain a target command signal, wherein the initial command signal is generated based on an Error Check and Scrub (ECS) operation mode, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation, and the target command signal is used for performing a second operation;
wherein the initial command signal comprises an activate signal, and the target command signal comprises a read signal, or
the initial command signal comprises a read signal, and the target command signal comprises a write signal, or
the initial command signal comprises a write signal, and the target command signal comprises a precharge signal,
wherein the activate signal is used for performing an activate operation, the read signal is used for performing a read operation, the write signal is used for performing a write operation, and the precharge signal is used for performing a precharge operation.