ELECTRONIC CIRCUIT WITH MOS TRANSISTORS AND MANUFACTURING METHOD

1 . An electronic circuit, comprising a plurality of transistors including:

at least one first MOS transistor of a first conductivity type arranged inside and on top of at least one first active area of a semiconductor substrate;

at least one second MOS transistor of the second conductivity type arranged inside and on top of at least one second active area of the semiconductor substrate;

each first active area being delimited by a first insulating region which is recessed with respect to a first surface of the semiconductor substrate by a first depth; and

each second active area being delimited by a second insulating region which is flush with the first surface of the semiconductor substrate, or which is recessed with respect to the first surface of the semiconductor substrate by a second depth smaller than the first depth.

2 . The electronic circuit according to claim 1 , wherein the first surface of the semiconductor substrate is topped with gate regions of the at least one first MOS transistor and of the at least one second MOS transistor, each gate region being insulated from the semiconductor substrate by a gate insulator layer.

3 . The electronic circuit according to claim 1 , wherein the at least one first and one second insulating regions are shallow trench insulations.

4 . The electronic circuit according to claim 1 , wherein the at least one first and one second insulating regions are adjacent to each other.

5 . The electronic circuit according to claim 1 , wherein the first depth is greater than or equal to 120 Å, and the second depth is smaller than 120 Å.

6 . The electronic circuit according to claim 1 , wherein the gate region of at least one transistor among the plurality of transistors includes at least one counter-doping area of a conductivity type opposite to the conductivity type of said at least one transistor, said at least one counter-doping area being positioned and sized to attenuate the hump effect of said at least one transistor, said at least one counter-doping area being positioned at the level of an overlapping area between the gate region and the active area of said at least one transistor.

7 . The electronic circuit according to claim 6 , wherein the at least one transistor is the at least one first MOS transistor.

8 . The electronic circuit according to claim 1 , wherein the first conductivity type is type N, each first MOS transistor being an NMOS transistor, and the second conductivity type is type P, each second MOS transistor being a PMOS transistor.

9 . The electronic circuit according to claim 1 , wherein the semiconductor substrate includes silicon and the at least one first and one second insulating regions include silicon oxide.

10 . The electronic circuit according to claim 1 , wherein the electronic circuit is contained in an electrically erasable and programmable non-volatile memory.

11 . A method, comprising:

forming a first trench insulation in a semiconductor substrate delimiting a first active area of the semiconductor substrate;

forming a second trench insulation in the semiconductor substrate delimiting a second active area of the semiconductor substrate;

recessing a top surface of the first trench insulation to a first depth below a top surface of the semiconductor substrate;

recessing a top surface of the second trench insulation to a second depth below the top surface of the semiconductor substrate;

forming a first MOS transistor of a first conductivity type at the first active region; and

forming a second MOS transistor of a second conductivity type at the second active region.

12 . The method according to claim 11 , comprising recessing the top surface of the second trench insulation after recessing the top surface of the first trench insulation.

13 . The method according to claim 11 , comprising:

forming the first and second trench insulations in a same process;

recessing the top surface of the first trench insulation to the first depth with a first etching process; and

recessing the top surface of the second trench insulation to the second depth with a second etching process after the first etching process while the first trench insulation is covered by a first mask and the second trench insulation is exposed through the first mask.

14 . The method according to claim 13 , wherein the first and second trench insulations are exposed to the first etching process through a second mask.

15 . The method according to claim 11 , wherein the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor.

16 . The method according to claim 15 , wherein the first trench insulation abuts the second trench insulation.

17 . An integrated circuit, comprising:

a semiconductor substrate including a first active area and a second active area;

a first transistor of a first conductivity type at the first active region;

a second transistor of a second conductivity type at the second active area; and

a trench insulation defining a boundary between the first active area and the second active area and including a top surface with a step such that a first portion of the top surface of the trench insulation next to the first active area is lower than a second portion of the top surface of the trench insulation than to next to the second active area.

18 . The integrated circuit according to claim 17 , wherein the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

19 . The integrated circuit according to claim 17 wherein the top surface of the trench insulation is below a top surface of the semiconductor substrate near the first active area, wherein the top surface of the trench insulation is substantially coplanar with the top surface of the semiconductor substrate near the second active area.

20 . The integrated circuit according to claim 17 , wherein the trench insulation is silicon oxide.