One-time programmable memory circuit, one-time programmable memory and operation method thereof
The present disclosure provides a one-time programmable memory, which includes a one-time programmable (OTP) diode and a control field effect transistor (FET). One end of the OTP diode is electrically connected to a source line. The control FET includes a gate, a first source/drain and a second source/drain, the gate of the control FET is electrically connected to a word line, the first source/drain of the control FET is electrically connected to a bit line, and the second source/drain of the control FET is electrically connected to another of the OTP diode.
1 . A one-time programmable (OTP) memory, comprising:
an OTP diode having one end electrically connected to a source line; and
a control field effect transistor (FET) comprising a gate, a first source/drain and a second source/drain, wherein the gate of the control FET is electrically connected to a word line, and the first source/drain of the control FET is electrically connected to a bit line, and the second source/drain of the control FET is electrically connected to another end of the OTP diode,
wherein the control FET is an N-type control FET or a P-type control FET, and the OTP diode is an NPN diode, a NIN diode, a gate-floating N-type FET, a PNP diode, a PIP diode or a gate-floating P-type FET.
2 . The one-time programmable memory of claim 1 , wherein when the control FET is turned on by a control voltage of the word line, a programming voltage of the bit line makes an avalanche breakdown occur in the OTP diode, thereby forming a programmed state of the OTP diode.
3 . A one-time programmable memory circuit, comprising:
a plurality of memory units arranged in an array, each of the memory units comprising a one-time programmable memory, and the one-time programmable memory comprising:
an OTP diode having one end electrically connected to a source line; and
a control FET comprising a gate, a first source/drain and a second source/drain, wherein the gate of the control FET is electrically connected to a word line, and the first source/drain of the control FET is electrically connected to a bit line, and the second source/drain of the control FET is electrically connected to another end of the OTP diode,
wherein the control FET is an N-type control FET or a P-type control FET, and the OTP diode is an NPN diode, a NIN diode, a gate-floating N-type FET, a PNP diode, a PIP diode or a gate-floating P-type FET.
4 . The one-time programmable memory circuit of claim 3 , wherein each of the memory units further comprises another one-time programmable memory, and the another one-time programmable memory comprises:
another OTP diode having one end electrically connected to a source line; and
another control FET comprising a gate, a first source/drain and a second source/drain, wherein the gate of the another control FET is electrically connected to another word line, the first source/drain of the another control FET is electrically connected to the bit line, and the second source/drain of the another control FET is electrically connected to another end of the another OTP diode.
5 . An operation method of a one-time programmable memory, the one-time programmable memory comprising an OTP diode and a control FET connected in series, and the operation method comprising steps of:
when programming the one-time programmable memory, applying a control voltage to a word line, applying a programming voltage to a bit line, and applying a zero voltage to a source line, wherein one end of the OTP diode is electrically connected to the source line, a gate of the control FET is electrically connected to the word line, a first source/drain of the control FET is electrically connected to the bit line, a second source/drain of the control FET is electrically connected to another end of the OTP diode,
wherein the control FET is an N-type control FET or a P-type control FET, and the OTP diode is an NPN diode, a NIN diode, a gate-floating N-type FET, a PNP diode, a PIP diode or a gate-floating P-type FET.
6 . The operation method of claim 5 , wherein the control voltage turns on the control FET, the programming voltage makes an avalanche breakdown occur in the OTP diode, thereby forming a programmed state of the OTP diode.
7 . The operation method of claim 5 , further comprising:
when reading the one-time programmable memory, applying a working voltage to the word line, applying the zero voltage to the source line, and applying a read voltage to the bit line.