IP Library Patent Application 18542991
Patent Application
App. No. 18/542,991

METHOD FOR FORMING SEMICONDUCTOR DIE AND SEMICONDUCTOR DEVICE THEREOF

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
18/542,991
Abstract

A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.

Claims (15)

1 . A semiconductor device, comprising:

a substrate;

an interlayer dielectric layer on the substrate;

a metal pad and a test pad on the interlayer dielectric layer; and

a passivation dielectric layer formed on the interlayer dielectric layer, the metal pad, and the test pad, and patterned to expose a portion of the metal pad and the test pad,

wherein portions of the interlayer dielectric layer on both sides of the test pad are etched to expose the substrate.

2 . The device of claim 1 , wherein the interlayer dielectric layer comprises:

a first interlayer dielectric layer on the substrate; and

a second interlayer dielectric layer on the first interlayer dielectric layer, and

wherein a metal wire is formed on the first interlayer dielectric layer.

3 . The device of claim 2 , wherein the first interlayer dielectric layer is a low-k dielectric layer.

4 . The device of claim 2 , wherein the first interlayer dielectric layer and the second interlayer dielectric layer are the same dielectric layer.

5 . The device of claim 2 , wherein the second interlayer dielectric layer has a higher dielectric constant value than the first interlayer dielectric layer.

6 . The device of claim 1 , further comprising a bump connected to the metal pad.

7 . The device of claim 1 , wherein after the portions of the interlayer dielectric layer are etched, another portion of the interlayer dielectric layer exists on the substrate at a predetermined thickness.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2025
From: MAGNACHIP MIXED-SIGNAL, LTD.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 071813/0800 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2024
From: JEONG, JIN WON; LEE, JANG HEE; JUN, YOUNG HUN; LEE, JONG WOON; CHOI, JAE SIK
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 066938/0308 →
NUNC PRO TUNC ASSIGNMENT Recorded Mar 14, 2024
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: MAGNACHIP MIXED-SIGNAL, LTD.
Reel/Frame 066878/0875 →