Systems and methods for power switch control for inverter for electric vehicle
A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a power switch including a gate terminal; and a gate driver configured to: receive a pulse to control an operation of the power switch, generate, based on the received pulse, a first signal to the gate terminal to increase a gate voltage level of the power switch at a first rate from an off-state gate voltage level to a first on-state gate voltage level in a first time period, and generate, based on the received pulse, a second signal to the gate terminal to increase the gate voltage level of the power switch at a second rate, less than the first rate, to a second on-state gate voltage level in a second time period subsequent to the first time period.
1 . A system comprising:
an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes:
a power switch including a gate terminal; and
a gate driver configured to:
receive a pulse to control an operation of the power switch,
generate, based on the received pulse, a first signal to the gate terminal to increase a gate voltage level of the power switch at a first rate from an off-state gate voltage level to a first on-state gate voltage level in a first time period, and
generate, based on the received pulse, a second signal to the gate terminal to increase the gate voltage level of the power switch at a second rate, less than the first rate, to a second on-state gate voltage level in a second time period subsequent to the first time period, wherein the second time period is subsequent to a settling of a ringing phase at the gate terminal of the power switch, wherein the ringing phase is caused by the generated first signal.
2 . The system of claim 1 , wherein the first rate is configured to cause the power switch to transition from the off-state gate voltage level to the first on-state gate voltage level in less than 1 μs.
3 . The system of claim 1 , wherein the second rate is configured to cause the power switch to increase to the second on-state gate voltage level with reduced oscillations relative to oscillations of the gate voltage level of the power switch in the first time period.
4 . The system of claim 1 , wherein the gate driver is further configured to:
generate, based on the received pulse, a third signal to the gate terminal to decrease the gate voltage level of the power switch from the first on-state gate voltage level to a third on-state gate voltage level, lower than the first on-state gate voltage level, in a third time period subsequent to the first time period and preceding the second time period.
5 . The system of claim 4 , wherein the second signal is configured to increase the gate voltage level of the power switch from the third on-state gate voltage level to the second on-state gate voltage level.
6 . The system of claim 4 , wherein the third signal is configured to cause the power switch to decrease to the third on-state gate voltage level to avoid an overshoot of the gate voltage level of the power switch above a maximum rated gate voltage level of the power switch.
7 . The system of claim 1 , wherein the gate driver is further configured to:
generate, based on the received pulse, a fourth signal to the gate terminal to decrease the gate voltage level of the power switch from the second on-state gate voltage level to the off-state gate voltage level in a fourth time period subsequent to the second time period.
8 . The system of claim 1 , further comprising:
the battery configured to supply the DC power to the inverter; and
the motor configured to receive the AC power from the inverter to drive the motor.
9 . The system of claim 8 , further comprising:
an electric vehicle including the battery, the inverter, and the motor.
10 . A system comprising:
a power switch driver configured to:
receive a pulse to control an operation of a power switch,
generate, based on the received pulse, a first signal to the power switch to increase a gate voltage level of the power switch at a first rate from an off-state gate voltage level to a first on-state gate voltage level in a first time period, and
generate, based on the received pulse, a second signal to the power switch to increase the gate voltage level of the power switch at a second rate, less than the first rate, to a second on-state gate voltage level in a second time period subsequent to the first time period,
wherein the power switch driver includes one or more of:
one or more diodes to control flow of current from an external power supply, or
one or more resistors to control the first rate and the second rate.
11 . The system of claim 10 , wherein:
the first rate is at least 22V/1 μs, and
the second rate is approximately 3V/8 μs.
12 . The system of claim 10 , wherein the power switch driver is an external waveform controller for a gate driver.
13 . The system of claim 10 , wherein the power switch driver includes one or more power supplies to generate one or more of the first signal or the second signal.
14 . The system of claim 10 , wherein the power switch driver includes one or more switches to generate one or more of the first signal or the second signal.
15 . A system comprising:
a gate driver configured to receive a pulse to control an operation of a power switch, and generate a gate signal based on the pulse; and
a waveform controller configured to:
receive the gate signal from the gate driver,
generate, based on the received gate signal, a first signal to the power switch to increase a gate voltage level of the power switch at a first rate from an off-state gate voltage level to a first on-state gate voltage level in a first time period, and
generate, based on the received gate signal, a second signal to the power switch to increase the gate voltage level of the power switch at a second rate, less than the first rate, to a second on-state gate voltage level in a second time period subsequent to the first time period,
wherein the second rate is configured to cause the power switch to increase to the second on-state gate voltage level with reduced oscillations relative to oscillations of the gate voltage level of the power switch in the first time period.
16 . The system of claim 15 , wherein the waveform controller includes one or more electrical hardware components to control a time delay between an initial rise in the gate voltage level of the power switch to the first on-state gate voltage level and a subsequent rise in the gate voltage level of the power switch to the second on-state gate voltage level.
17 . The system of claim 15 , wherein the waveform controller includes one or more electrical hardware components to control the second rate.