IP Library › Granted Patent US 12,204,991
Granted Patent B1
US 12,204,991 · App. 18/543,596 · Granted Jan 21, 2025

Gate formation on a quantum processor

Inventors: Colm Andrew Ryan (Albany, CA); Eric Christopher Peterson (Miami, FL); Marcus Palmer da Silva (Lafayette, CA); Michael Justin Gerchick Scheer (Oakland, CA); Deanna Margo Abrams (Oakland, CA)
Assignee: Rigetti & Co, LLC
G06N10/00G06F9/4843G06F16/2379H03K19/195
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Quick Facts
Patent No.
US 12,204,991
App. No.
18/543,596
Granted
Jan 21, 2025
Kind
B1
Abstract

In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Claims (61)

1. A computing method comprising:

receiving a program comprising a first sequence of quantum logic gates, the first sequence comprising a first parametric multi-qubit quantum logic gate;

identifying a native gate set comprising a set of quantum logic gates associated with a quantum processor unit;

identifying a second sequence of quantum logic gates corresponding to the first parametric multi-qubit quantum logic gate, each of the quantum logic gates in the second sequence being selected from the native gate set, the second sequence comprising a second parametric quantum logic gate;

generating a native program comprising a third sequence of quantum logic gates, the third sequence of quantum logic gates corresponding to the first sequence of quantum logic gates and comprising the second sequence of quantum logic gates; and

providing the native program for execution by the quantum processor unit.

2. The method of claim 1 , wherein identifying the second sequence comprises:

determining a value of a variable parameter specified by the first parametric multi-qubit quantum logic gate; and

assigning the value to a variable parameter of one or more of the quantum logic gates in the second sequence.

3. The method of claim 1 , wherein each of the first parametric multi-qubit quantum logic gate and the second parametric quantum logic gate is a first type of parametric multi-qubit quantum logic gate, the first type of parametric multi-qubit quantum logic gate comprises a first variable parameter, the program assigns a first value to the first variable parameter, and the native program assigns a second, different value to the first variable parameter.

4. The method of claim 3 , wherein the first type of multi-qubit quantum logic gate comprises the first variable parameter and a second variable parameter, the program assigns a third value to the second variable parameter, and the native program assigns the third value to the second variable parameter.

5. The method of claim 3 , wherein the second sequence of quantum logic gates further comprises a parametric single-qubit quantum logic gate.

6. The method of claim 1 , wherein the second sequence of quantum logic gates comprises a second parametric multi-qubit quantum logic gate and parametric single-qubit rotation gates, and identifying the second sequence of quantum logic gates comprises determining rotation angles for the parametric single-qubit rotation gates.

7. The method of claim 6 , wherein determining the rotation angles comprises retrieving the rotation angles from a database.

8. The method of claim 6 , wherein the quantum processor unit is configured to execute the parametric single-qubit rotation gates as frame adjustments.

9. The method of claim 1 , wherein identifying the second sequence of quantum logic gates comprises:

decomposing, by operation of a just-in-time compiler, the first parametric multi-qubit quantum logic gate into the second sequence of quantum logic gates based on a predetermined parametric circuit database and a predetermined pulse calibration database.

10. The method of claim 1 , wherein identifying the second sequence of quantum logic gates comprises:

decomposing, by operation of a userland compiler, the first parametric multi-qubit quantum logic gate into the second sequence of quantum logic gates by executing a parametric decomposition process.

11. The method of claim 10 , wherein providing the native program for execution by the quantum processor unit comprises sending the native program to a computing environment that comprises the quantum processor unit, and the computing environment comprises a just-in-time compiler configured to apply a pulse calibration to the native program.

12. The method of claim 1 , further comprising generating a binary program based on the native program, and executing the binary program on the quantum processor unit.

13. The method of claim 12 , wherein the quantum processor unit comprises a superconducting quantum processor circuit comprising a plurality of qubit devices.

14. The method of claim 13 , wherein the second parametric quantum logic gate comprises a two-qubit quantum logic gate applied to a pair of qubits defined by a tunable-frequency qubit device and a fixed-frequency qubit device.

15. The method of claim 1 , wherein the second sequence of quantum logic gates comprises at least one of: a single-qubit parametric rotation gate, a two-qubit parametric interaction gate, a controlled parametric rotation gate, a controlled two-qubit parametric interaction.

16. The method of claim 1 , wherein the second sequence of quantum logic gates further comprises a non-parametric quantum logic gate.

17. The method of claim 1 , wherein the first parametric multi-qubit quantum logic gate comprises a first parametric two-qubit quantum logic gate, and the second parametric quantum logic gate comprises a second parametric two-qubit quantum logic gate.

18. The method of claim 17 , wherein the first parametric multi-qubit quantum logic gate comprises a Controlled-Phase (CPHASE) gate.

19. The method of claim 17 , wherein the first parametric multi-qubit quantum logic gate comprises a Toffoli gate.

20. The method of claim 1 , wherein the first parametric multi-qubit quantum logic gate comprises a first parametric three-qubit quantum logic gate.

21. The method of claim 20 , wherein the first parametric three-qubit quantum logic gate comprises a Controlled-Controlled-Phase (CCPHASE) gate.

22. The method of claim 1 , wherein the second sequence of quantum logic gates comprises a plurality of parametric two-qubit quantum logic gates.

23. The method of claim 1 , wherein the first parametric multi-qubit quantum logic gate comprises a first parametric two-qubit quantum logic gate, and the second parametric quantum logic gate comprises a parametric single-qubit quantum logic gate.

24. A computing system comprising:

a quantum processor unit; and

a compiler configured to:

receiving a program comprising a first sequence of quantum logic gates, the first sequence comprising a first parametric multi-qubit quantum logic gate;

identifying a native gate set comprising a set of quantum logic gates associated with a quantum processor unit;

identifying a second sequence of quantum logic gates corresponding to the first parametric multi-qubit quantum logic gate, each of the quantum logic gates in the second sequence being selected from the native gate set, the second sequence comprising a second parametric quantum logic gate;

generating a native program comprising a third sequence of quantum logic gates, the third sequence of quantum logic gates corresponding to the first sequence of quantum logic gates and comprising the second sequence of quantum logic gates; and

providing the native program for execution by the quantum processor unit.

25. The system of claim 24 , wherein each of the first parametric multi-qubit quantum logic gate and the second parametric quantum logic gate is a first type of parametric multi-qubit quantum logic gate, the first type of parametric multi-qubit quantum logic gate comprises a first variable parameter, the program assigns a first value to the first variable parameter, and the native program assigns a second, different value to the first variable parameter.

26. The system of claim 25 , wherein the first type of multi-qubit quantum logic gate comprises the first variable parameter and a second variable parameter, the program assigns a third value to the second variable parameter, and the native program assigns the third value to the second variable parameter.

27. The system of claim 25 , wherein the second sequence of quantum logic gates further comprises a parametric single-qubit quantum logic gate.

28. The system of claim 24 , wherein the second sequence of quantum logic gates comprises a second parametric multi-qubit quantum logic gate and parametric single-qubit rotation gates, and identifying the second sequence of quantum logic gates comprises determining rotation angles for the parametric single-qubit rotation gates.

29. The system of claim 28 , wherein the rotation angles are determined by retrieving the rotation angles from a database.

30. The system of claim 28 , wherein the quantum processor unit is configured to execute the parametric single-qubit rotation gates as frame adjustments.

31. The system of claim 24 , wherein the second sequence of quantum logic gates is identified by decomposing the first parametric multi-qubit quantum logic gate into the second sequence of quantum logic gates based on a predetermined parametric circuit database and a predetermined pulse calibration database.

32. The system of claim 24 , comprising:

a control system configured to:

generate a binary program based on the native program, and executing the binary program on the quantum processor unit.

33. The system of claim 24 , wherein the quantum processor unit comprises a superconducting quantum processor circuit comprising a plurality of qubit devices.

34. The system of claim 33 , wherein the second parametric quantum logic gate comprises a two-qubit quantum logic gate applied to a pair of qubits defined by a tunable-frequency qubit device and a fixed-frequency qubit device.

35. The system of claim 24 , wherein the second sequence of quantum logic gates comprises at least one of: a single-qubit parametric rotation gate, a two-qubit parametric interaction gate, a controlled parametric rotation gate, a controlled two-qubit parametric interaction.

36. The system of claim 24 , wherein the second sequence of quantum logic gates further comprises a non-parametric quantum logic gate.

37. The system of claim 24 , wherein the first parametric multi-qubit quantum logic gate comprises a first parametric two-qubit quantum logic gate, and the second parametric quantum logic gate comprises a second parametric two-qubit quantum logic gate.

38. The system of claim 37 , wherein the first parametric multi-qubit quantum logic gate comprises a Controlled-Phase (CPHASE) gate.

39. The system of claim 37 , wherein the first parametric multi-qubit quantum logic gate comprises a Toffoli gate.

40. The system of claim 24 , wherein the first parametric multi-qubit quantum logic gate comprises a first parametric three-qubit quantum logic gate.

41. The system of claim 40 , wherein the first parametric three-qubit quantum logic gate comprises a Controlled-Controlled-Phase (CCPHASE) gate.

42. The system of claim 24 , wherein the second sequence of quantum logic gates comprises a plurality of parametric two-qubit quantum logic gates.

43. The system of claim 24 , wherein the first parametric multi-qubit quantum logic gate comprises a first parametric two-qubit quantum logic gate, and the second parametric quantum logic gate comprises a parametric single-qubit quantum logic gate.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2024
From: TRINITY CAPITAL INC.
To: RIGETTI & CO, LLC
Reel/Frame 069603/0771 →
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2024
From: TRINITY CAPITAL INC.
To: RIGETTI & CO, LLC; RIGETTI INTERMEDIATE LLC; RIGETTI COMPUTING, INC.
Reel/Frame 069603/0831 →
AMENDED AND RESTATED INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Jul 8, 2024
From: RIGETTI & CO, LLC; RIGETTI INTERMEDIATE LLC; RIGETTI COMPUTING, INC.
To: TRINITY CAPITAL INC.
Reel/Frame 068146/0416 →
CHANGE OF NAME Recorded Jan 22, 2024
From: RIGETTI & CO., INC.
To: RIGETTI & CO, LLC
Reel/Frame 066358/0634 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2024
From: RYAN, COLM ANDREW; PETERSON, ERIC CHRISTOPHER; DA SILVA, MARCUS PALMER; SCHEER, MICHAEL JUSTIN GERCHICK; ABRAMS, DEANNA MARGO
To: RIGETTI & CO., INC.
Reel/Frame 066176/0189 →
Continuity (4)
Continuation 18155909 · Jan 18, 2023
Continuation 17074124 · Oct 19, 2020
Provisional Application 62923275 · Oct 18, 2019
Provisional Application 62944494 · Dec 6, 2019
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Cited By (2)
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