Acoustic noise suppression in PFM based buck regulator
The present disclosure provides an approach that determines a pulse frequency modulation (PFM) period of a buck regulator. The PFM period comprises a first charging stage and a first discharging stage, and wherein the buck regulator switches from the first discharging stage to the first charging stage based on comparing a feedback voltage to a low threshold voltage. The approach generates a pseudo random pulse at a pseudo random period, wherein the pseudo random period is independent from the low threshold voltage. Then, the approach initiates a transition from a second discharging stage to a second charging stage based on the pseudo random pulse.
1 . A method comprising:
determining a pulse frequency modulation (PFM) period of a buck regulator, wherein the PFM period comprises a first charging stage and a first discharging stage, and wherein the buck regulator switches from the first discharging stage to the first charging stage based on comparing a feedback voltage to a low threshold voltage;
generating, by a processing device, a pseudo random pulse at a pseudo random period, wherein the pseudo random period is independent from the low threshold voltage; and
initiating a transition from a second discharging stage to a second charging stage based on the pseudo random pulse.
2 . The method of claim 1 , further comprising:
generating the pseudo random pulse in response to determining that the PFM period corresponds to a PFM frequency within an audible frequency range.
3 . The method of claim 1 , further comprising:
capturing a plurality of PFM periods of the buck regulator comprising the PFM period;
computing an average PFM period based on the plurality of PFM periods;
generating a pseudo random number; and
computing the pseudo random period based on the pseudo random number and the average PFM period.
4 . The method of claim 3 , further comprising:
generating a new pseudo random number;
computing a new pseudo random period based on the new pseudo random number and the average PFM period;
generating a new pseudo random pulse based on the new pseudo random period, wherein the new pseudo random period is a different time duration than the pseudo random period; and
initiating a new transition from a third discharging stage to a third charging stage based on the new pseudo random pulse.
5 . The method of claim 1 , the method further comprising:
providing the pseudo random pulse to a first input of OR logic, wherein the OR logic produces an OR logic output that selects a high threshold voltage as an input to a comparator;
comparing, by the comparator, the high threshold voltage to the feedback voltage; and
producing, by the comparator, a comparator output that initiates the transition from the second discharging stage to the second charging stage based comparing the high threshold voltage to the feedback voltage.
6 . The method of claim 5 , wherein the comparator output feeds to a second input of the OR logic, and wherein the OR logic output selects the low threshold voltage as the input to the comparator when the feedback voltage reaches the high threshold voltage.
7 . The method of claim 1 , wherein the buck regulator switches from the second discharging stage to the second charging stage prior to the feedback voltage reaching the low threshold voltage.
8 . A system comprising:
a processing device; and
a memory to store instructions that, when executed by the processing device cause the system to:
determine a pulse frequency modulation (PFM) period of a buck regulator, wherein the PFM period comprises a first charging stage and a first discharging stage, and wherein the buck regulator switches from the first discharging stage to the first charging stage based on comparing a feedback voltage to a low threshold voltage;
generate a pseudo random pulse at a pseudo random period, wherein the pseudo random period is independent from the low threshold voltage; and
initiate a transition from a second discharging stage to a second charging stage based on the pseudo random pulse.
9 . The system of claim 8 , wherein the processing device, responsive to executing the instructions, further causes the system to:
generate the pseudo random pulse in response to determining that the PFM period corresponds to a PFM frequency within an audible frequency range.
10 . The system of claim 8 , wherein the processing device, responsive to executing the instructions, further causes the system to:
capture a plurality of PFM periods of the buck regulator comprising the PFM period;
compute an average PFM period based on the plurality of PFM periods;
generate a pseudo random number; and
compute the pseudo random period based on the pseudo random number and the average PFM period.
11 . The system of claim 10 , wherein the processing device, responsive to executing the instructions, further causes the system to:
generate a new pseudo random number;
compute a new pseudo random period based on the new pseudo random number and the average PFM period;
generate a new pseudo random pulse based on the new pseudo random period, wherein the new pseudo random period is a different time duration than the pseudo random period; and
initiate a new transition from a third discharging stage to a third charging stage based on the new pseudo random pulse.
12 . The system of claim 8 , wherein the processing device, responsive to executing the instructions, further causes the system to:
provide the pseudo random pulse to a first input of OR logic, wherein the OR logic produces an OR logic output that selects a high threshold voltage as an input to a comparator;
compare, by the comparator, the high threshold voltage to the feedback voltage; and
produce, by the comparator, a comparator output that initiates the transition from the second discharging stage to the second charging stage based comparing the high threshold voltage to the feedback voltage.
13 . The system of claim 12 , wherein the comparator output feeds to a second input of the OR logic, and wherein the OR logic output selects the low threshold voltage as the input to the comparator when the feedback voltage reaches the high threshold voltage.
14 . The system of claim 8 , wherein the buck regulator switches from the second discharging stage to the second charging stage prior to the feedback voltage reaching the low threshold voltage.
15 . The system of claim 8 , wherein the system is a cable compatible with a Universal Serial Bus Type-C (USB Type-C) specification.
16 . A power converter, comprising:
a buck regulator; and
controller circuitry, operatively coupled with the buck regulator, configured to:
determine a pulse frequency modulation (PFM) period of the buck regulator, wherein the PFM period comprises a first charging stage and a first discharging stage;
generate a pseudo random pulse at a pseudo random period; and
comparator circuitry to initiate a transition from a second discharging stage to a second charging stage based on the pseudo random pulse.
17 . The power converter of claim 16 , wherein the controller is further configured to:
generate the pseudo random pulse in response to determining that the PFM period corresponds to a PFM frequency within an audible frequency range.
18 . The power converter of claim 16 , wherein the controller is further configured to:
capture a plurality of PFM periods of the buck regulator comprising the PFM period;
compute an average PFM period based on the plurality of PFM periods;
generate a pseudo random number; and
compute the pseudo random period based on the pseudo random number and the average PFM period.
19 . The power converter of claim 17 , wherein the controller is further configured to:
generate a new pseudo random number;
compute a new pseudo random period based on the new pseudo random number and 9
generate a new pseudo random pulse based on the new pseudo random period, wherein the new pseudo random period is a different time duration than the pseudo random period; and
initiate a new transition from a third discharging stage to a third charging stage based on the new pseudo random pulse.
20 . The power converter of claim 16 , wherein the comparator circuitry further comprises:
OR logic circuitry, wherein the OR logic circuitry is configured to receive the pseudo random pulse at a first input and produce an OR logic output that selects a high threshold voltage; and
a comparator configured to:
receive the high threshold voltage as a input;
compare the high threshold voltage to a feedback voltage of the buck regulator; and
produce a comparator output that initiates the transition from the second discharging stage to the second charging stage based comparing the high threshold voltage to the feedback voltage.
21 . The power converter of claim 20 , wherein the comparator output feeds to a second input of the OR logic circuitry, and wherein the OR logic output selects a low threshold voltage as the input to the comparator when the feedback voltage reaches the high threshold voltage.
22 . The power converter of claim 16 , wherein the power converter is compatible with a Universal Serial Bus Power Delivery (USB-PD) specification.