IP Library Granted Patent US 12,573,939
Granted Patent B2
US 12,573,939 · App. 18/561,993 · Granted Mar 10, 2026

System and method for zero voltage switching in a power converter

Inventors: Jyrki Penttonen (Helsinki, FI); Natan Baron-Trocellier (Espoo, FI)
Assignee: Vensum Power Oy
H02M1/0058H02M1/0009H02M1/0012H02M3/158H02M7/219
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Quick Facts
Patent No.
US 12,573,939
App. No.
18/561,993
Granted
Mar 10, 2026
Kind
B2
Abstract

Disclosed is a system for zero voltage switching in a power converter with a first half-bridge and a second half-bridge. The first half-bridge has a first set of transistors and output inductor. The second half-bridge has a second set of transistors and auxiliary inductor. A current sensing means measures, at switching cycle scale, average and maximum current values of output inductor and average, minimum and maximum current values of auxiliary inductor. A voltage sensing means measures input and output voltages of first and second half-bridge. A controller is configured to compute dead times of pulse width modulation control signal of second half-bridge, generate pulse width modulation control signal of second half-bridge and to adapt dead times of first half-bridge.

Claims (42)

1 . A system for zero-voltage switching in a power converter comprising

a first half-bridge and a second half-bridge, wherein

the first half-bridge comprises a first set of transistors and an output inductor connected to a switching node of the first set of transistors, forming thereat a first circuit, and

the second half-bridge comprises a second set of transistors and an auxiliary inductor connected to a switching node of the second set of transistors and to the switching node of the first set of transistors, forming thereat a second circuit;

wherein the system further comprises

a current sensing means configured to measure, at switching cycle scale, an average and a maximum current values of the output inductor and an average, a minimum and a maximum current values of the auxiliary inductor;

a voltage sensing means configured to measure input and output voltages of the first half-bridge and the second half-bridge, and

a controller configured to compute dead times of pulse width modulation control signal of the second half-bridge, generate pulse width modulation control signal of the second half-bridge and to adapt dead times of the first half-bridge,

wherein the controller is configured to:

calculate a target average, a minimum and a maximum current values of an auxiliary inductor based on the measured input and output voltage and the output current values;

compute, based on the calculated target average, a minimum and a maximum current values of the auxiliary inductor, a rising dead time and a falling dead time of pulse width modulation control signal for a first half-bridge and for a second half-bridge;

compute, based on the target minimum and maximum values for the auxiliary inductor current, on the measured value for the input voltage of the first bridge, and on the calculated rising and falling dead times of the first half-bridge and the second half-bridge, a shift to apply; and

compute, based on the target value for the auxiliary inductor current, on the measured value for the input voltage of the first half-bridge, and on the calculated values for the dead times of the first and the second half-bridges, a duty cycle differential to apply.

2 . The system according to claim 1 , wherein the output inductor is configured to:

discharge a stray capacitance of a closing transistor of the first set of transistors;

charge a stray capacitance of an opening transistor of the first set of transistors.

3 . The system according to claim 1 , wherein the second half-bridge is configured to

drive a current of the switching node of the first half-bridge to a desired value before each of its transitions;

control the current of the auxiliary inductor.

4 . The system according to claim 1 , wherein the auxiliary inductor is configured to perform zero voltage switching in the first half-bridge and in the second half-bridge.

5 . The system according to claim 1 , wherein inductance of the auxiliary inductor is smaller than inductance of the output inductor.

6 . The system according to claim 1 , wherein a waveform shape of the current of the auxiliary inductor is determined by switching the second half-bridge with respect to the first half-bridge.

7 . A method for zero-voltage switching in a power converter, wherein the method comprising

measuring an input voltage and an output voltage values of a first half-bridge and of a second half-bridge of a system;

measuring an average and a maximum output current values of an output inductor;

calculating a target average, a minimum and a maximum current values of an auxiliary inductor based on the measured input and output voltage and the output current values;

computing, based on the calculated target average, minimum and maximum current values of the auxiliary inductor, a rising dead time and a falling dead time of pulse width modulation control signal for a first half-bridge and for a second half-bridge;

computing, based on the target minimum and maximum values for the auxiliary inductor current, on the measured value for the input voltage of the first bridge, and on the calculated rising and falling dead times of the first half-bridge and the second half-bridge a shift to apply;

computing, based on the target value for the auxiliary inductor current, on the measured value for the input voltage of the first half-bridge, and on the calculated values for the dead times of the first and the second half-bridges, a duty cycle differential to apply.

8 . The method according to claim 7 , wherein computing the optimal dead times comprises

computing for the second half-bridge the rising dead time as a function of the input voltage and the minimum current value of the auxiliary inductor, and the falling dead time as a function of the input voltage and the maximum current value of the auxiliary inductor;

computing for the first half-bridge computing the rising dead time as a function of the input and output voltage, the average and maximum output current, and the maximum current value of the auxiliary inductor, and the falling dead time as a function of the input and output voltages, the average and maximum output current, and the minimum current value of the auxiliary inductor.

9 . The method according to claim 7 , wherein computing the shift as function of the computed minimum and maximum current values of the auxiliary inductor, and of the input voltage.

10 . The method according to claim 9 , wherein computing the shift comprises incrementing the shift by a quantity dt.

11 . The method according to claim 7 , wherein computing the duty cycle differential comprises using a dynamical model of the average current value of the auxiliary inductor I aux =F(s)·(δD+c(transitions)).

12 . The method according to claim 7 , wherein generating the pulse width modulation control signal of the second half-bridge comprises

copying the pulse width modulation control signal of the first half-bridge;

setting the amplitude of the current of the auxiliary inductor;

setting the average current of the auxiliary inductor.

13 . The method according claim 7 , wherein generating the pulse width modulation control signal of the second half-bridge is based on a switching period, a duty cycle, a shift and a duty cycle differential parameters.

14 . The method according to claim 7 , wherein generating the pulse width modulation control signal of the second half-bridge is based on hysteresis control.

15 . The method according to claim 7 , wherein the method further comprises applying the zero-voltage switching in a single-phase half-bridge converter, in a single phase full-bridge converter or in a three phased boost inverter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2023
From: BARON-TROCELLIER, NATAN
To: VENSUM POWER OY
Reel/Frame 065602/0729 →
Priority Claims (1)
FI 20215586 · May 18, 2021 · national
Continuity (1)
Related Publication 20240250600A1 · Jul 25, 2024
References Cited (11)
US 5568368A · Steigerwald et al. · 1996 [cited by applicant]
US 20070007933A1 · Chan et al. · 2007 [cited by applicant]
US 20100131219A1 · Kenly et al. · 2010 [cited by applicant]
US 20120105039A1 · Brown · 2012 [cited by applicant]
US 20140177300A1 · Lagorce et al. · 2014 [cited by applicant]
US 20190267895A1 · Masuda · 2019 [cited by examiner]
US 20210028690A1 · Fromme et al. · 2021 [cited by applicant]
WO 2017023982A1 · 2017 [cited by applicant]
WO 2019224431A1 · 2019 [cited by applicant]
European Patent Office, International Search Report and Written Opinion, Application No. PCT/FI2022/050302, Mailed Aug. 3, 2022, 15 pages. [cited by applicant]
Finnish Patent and Registration Office, Search Report, U.S. Appl. No. 20/215,586, Mailed Jan. 18, 2022, 1 page. [cited by applicant]