IP Library Granted Patent US 12,641,920
Granted Patent B2
US 12,641,920 · App. 18/563,665 · Granted May 26, 2026

Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Inventors: Seiji Ishimoto (Shizuoka, JP); Daiki Jinno (Shizuoka, JP)
Assignee: KOITO MANUFACTURING CO., LTD.
H10H20/811H10H20/01335H10H20/821
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Quick Facts
Patent No.
US 12,641,920
App. No.
18/563,665
Granted
May 26, 2026
Kind
B2
Abstract

A semiconductor light-emitting element includes a growth substrate, a plurality of columnar semiconductor layers formed on the growth substrate, a p-type embedded semiconductor layer that is in contact with side surfaces of the plurality of columnar semiconductor layers and that covers the columnar semiconductor layers, a tunnel junction layer formed on the embedded semiconductor layer, and an n-type semiconductor layer formed on the tunnel junction layer. A mesa structure is formed in the embedded semiconductor layer, the tunnel junction layer, and the n-type semiconductor layer. The tunnel junction layer is formed to extend up to a side surface of the mesa structure.

Claims (30)

1 . A semiconductor light-emitting element comprising:

a growth substrate;

a plurality of columnar semiconductor layers formed on the growth substrate;

a p-type embedded semiconductor layer that is in contact with side surfaces of the plurality of columnar semiconductor layers and that covers the columnar semiconductor layers;

a tunnel junction layer formed on the embedded semiconductor layer; and

an n-type semiconductor layer formed on the tunnel junction layer,

wherein a mesa structure is formed in the embedded semiconductor layer, the tunnel junction layer, and the n-type semiconductor layer, and

the tunnel junction layer is formed to extend up to a side surface of the mesa structure, and

the tunnel junction layer is formed with a groove reaching up from a surface of the mesa structure.

2 . The semiconductor light-emitting element according to claim 1 , wherein the tunnel junction layer has a stacked structure of an n+ layer and a p+ layer, and the groove reaches up to at least the p+ layer from the surface of the mesa structure.

3 . The semiconductor light-emitting element according to claim 2 ,

wherein the groove is formed to reach up to the embedded semiconductor layer.

4 . The semiconductor light-emitting element according to claim 3 ,

wherein the groove is formed to reach up to a growth substrate side with respect to a top surface of the columnar semiconductor layer.

5 . The semiconductor light-emitting element according to claim 1 ,

wherein the groove is formed in a region except for the columnar semiconductors, in a plan view.

6 . The semiconductor light-emitting element according to claim 1 ,

wherein the groove is formed in a dot shape or a linear shape.

7 . A method for manufacturing a semiconductor light-emitting element, the method comprising:

a first growth step of forming, on a growth substrate, a plurality of columnar semiconductor layers and a p-type embedded semiconductor layer;

a second growth step of forming, on the embedded semiconductor layer, a tunnel junction layer and an n-type semiconductor layer;

a mesa forming step of forming a mesa structure in the embedded semiconductor layer, the tunnel junction layer, and the n-type semiconductor layer to expose the tunnel junction layer from a side surface of the mesa structure; and

an activation step of activating a p+ layer included in the tunnel junction layer, after the mesa forming step.

8 . The method for manufacturing a semiconductor light-emitting element according to claim 7 , further comprising:

a groove etching step of forming, by etching, a groove that reaches up to at least the p+ layer from a surface of the mesa structure, after the second growth step and before the activation step.

9 . The method for manufacturing a semiconductor light-emitting element according to claim 7 ,

wherein the second growth step includes a groove mask removal step of:

forming a mask on a part of the embedded semiconductor layer;

growing the tunnel junction layer and the n-type semiconductor layer, by selective growth using the mask; and

removing the mask to form a groove, after the second growth step and before the activation step.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2023
From: ISHIMOTO, SEIJI; JINNO, DAIKI
To: KOITO MANUFACTURING CO., LTD.
Reel/Frame 065665/0214 →
Priority Claims (1)
JP 2021-089283 · May 27, 2021 · national
Continuity (1)
Related Publication 20240274749A1 · Aug 15, 2024
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