Granted Patent B2

US 12,647,897 · App. 18/574,565 · Granted Jun 2, 2026

Inventors: Na Chen (San Diego, CA); Su-Lin Low (San Diego, CA)

Assignee: Nokia Technologies Oy

H04W52/0287H04W80/02

Abstract

Claims (85)

1 . A baseband chip, comprising:

a data plane (DP) subsystem, comprising:

a DP clock generation unit configured to set a frequency level for the DP subsystem;

a DP power control unit configured to set a voltage level for the DP subsystem;

a microcontroller (uC) cluster comprising a DP frequency/voltage selection component configured to:

determine a frequency-level adjustment and a voltage-level adjustment associated with a slot based on a set of inputs;

configure the DP clock generation unit with the frequency-level adjustment; and

configure the DP power control unit with the voltage-level adjustment.

2 . The baseband chip of claim 1 , wherein, to determine the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs, the DP frequency/voltage selection component is configured to:

receive, by a minimum frequency-table adjustment unit, a set of static and semi-static inputs from a DP controller external to the DP subsystem;

generate, by the minimum frequency-table adjustment unit, a minimum frequency adjustment table based on the set of static and semi-static inputs; and

input, by the minimum frequency-table adjustment unit, the minimum frequency adjustment table into a minimum frequency-table look-up unit.

3 . The baseband chip of claim 2 , wherein the set of static and semi-static inputs includes one or more of a number of component carriers (CCs) associated with a grant, a maximum data throughput per slot and component carrier (CC), a slot duration per CC, an available DP subsystem frequency level, an available DP subsystem voltage level, a logical channel prioritization (LCP) processing rate, or a DP hardware cipher rate.

4 . The baseband chip of claim 2 , wherein, to determine the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs, the DP frequency/voltage selection component is configured to:

receive, by the minimum frequency-table look-up unit, the minimum frequency adjustment table from the minimum frequency-table adjustment unit;

receive, by the minimum frequency-table look-up unit, a first dynamic input from a physical layer (PHY) controller external to the DP subsystem, a second dynamic input from a logical channel prioritization (LCP) unit, and a third dynamic input from a Layer 2 parsing unit, the DP frequency/voltage selection component including the LCP unit and the Layer 2 parsing unit;

identify, by the minimum frequency-table look-up unit, the frequency-level adjustment based on the minimum frequency adjustment table and one or more of the first dynamic input, the second dynamic input, or the third dynamic input; and

input, by the minimum frequency-table look-up unit, the frequency-level adjustment into a frequency/voltage controller.

5 . The baseband chip of claim 4 , wherein:

the first dynamic input includes a grant size associated with the slot, a grant duration associated with the slot, or a PHY subsystem due time for an uplink packet associated with the slot,

the second dynamic input includes an average-UL packet size associated with the slot, and

the third dynamic input includes an average-DL packet size associated with the slot.

6 . The baseband chip of claim 4 , wherein, to determine the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs, the DP frequency/voltage selection component is configured to:

receive, by the frequency/voltage controller, the frequency-level adjustment from the minimum frequency-table look-up unit;

in response to determining that the frequency-level adjustment meets a frequency-up threshold value or a frequency-down threshold value, identifying a voltage-level adjustment based on the frequency-level adjustment; and

in response to determining that the frequency-level adjustment meets a frequency-up threshold value or a frequency-down threshold value, configure, by the frequency/voltage controller, the DP clock generation unit with the frequency-level adjustment and the DP power control unit with the voltage-level adjustment.

7 . The baseband chip of claim 6 , wherein:

the DP clock generation unit is configured to set a new frequency level for the DP subsystem based on the frequency-level adjustment configured by the frequency/voltage controller, and

the DP power control unit is configured to set a new voltage level for the DP subsystem based on the voltage-level adjustment configured by the frequency/voltage controller.

8 . An apparatus for a user equipment (UE), comprising:

a baseband chip, comprising:

a data plane (DP) subsystem, comprising:

a DP clock generation unit configured to set a frequency level for the DP subsystem;

a DP power control unit configured to set a voltage level for the DP subsystem;

a microcontroller (uC) cluster comprising a DP frequency/voltage selection component configured to:

determine a frequency-level adjustment and a voltage-level adjustment associated with a slot based on a set of inputs;

configure the DP clock generation unit with the frequency-level adjustment; and

configure the DP power control unit with the voltage-level adjustment.

9 . The apparatus of claim 8 , wherein, to determine the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs, the DP frequency/voltage selection component is configured to:

receive, by a minimum frequency-table adjustment unit, a set of static and semi-static inputs from a DP controller external to the DP subsystem;

generate, by the minimum frequency-table adjustment unit, a minimum frequency adjustment table based on the set of static and semi-static inputs; and

input, by the minimum frequency-table adjustment unit, the minimum frequency adjustment table into a minimum frequency-table look-up unit.

10 . The apparatus of claim 9 , wherein the set of static and semi-static inputs includes one or more of a number of component carriers (CCs) associated with a grant, a maximum data throughput per slot and component carrier (CC), a slot duration per CC, an available DP subsystem frequency level, an available DP subsystem voltage level, a logical channel prioritization (LCP) processing rate, or a DP hardware cipher rate.

11 . The apparatus of claim 9 , wherein, to determine the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs, the DP frequency/voltage selection component is configured to:

receive, by the minimum frequency-table look-up unit, the minimum frequency adjustment table from the minimum frequency-table adjustment unit;

receive, by the minimum frequency-table look-up unit, a first dynamic input from a physical layer (PHY) controller external to the DP subsystem, a second dynamic input from a logical channel prioritization (LCP) unit, and a third dynamic input from a Layer 2 parsing unit, the DP frequency/voltage selection component including the LCP unit and the Layer 2 parsing unit;

identify, by the minimum frequency-table look-up unit, the frequency-level adjustment based on the minimum frequency adjustment table and one or more of the first dynamic input, the second dynamic input, or the third dynamic input; and

input, by the minimum frequency-table look-up unit, the frequency-level adjustment into a frequency/voltage controller.

12 . The apparatus of claim 11 , wherein:

the first dynamic input includes a grant size associated with the slot, a grant duration associated with the slot, or a PHY subsystem due time for an uplink packet associated with the slot,

the second dynamic input includes an average-UL packet size associated with the slot, and

the third dynamic input includes an average-DL packet size associated with the slot.

13 . The apparatus of claim 11 , wherein, to determine the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs, the DP frequency/voltage selection component is configured to:

receive, by the frequency/voltage controller, the frequency-level adjustment from the minimum frequency-table look-up unit;

in response to determining that the frequency-level adjustment meets a frequency-up threshold value or a frequency-down threshold value, identifying a voltage-level adjustment based on the frequency-level adjustment; and

in response to determining that the frequency-level adjustment meets a frequency-up threshold value or a frequency-down threshold value, configure, by the frequency/voltage controller, the DP clock generation unit with the frequency-level adjustment and the DP power control unit with the voltage-level adjustment.

14 . The apparatus of claim 13 , wherein:

the DP clock generation unit is configured to set a new frequency level for the DP subsystem based on the frequency-level adjustment configured by the frequency/voltage controller, and

the DP power control unit is configured to set a new voltage level for the DP subsystem based on the voltage-level adjustment configured by the frequency/voltage controller.

15 . A method for configuration of a baseband chip, comprising:

setting, by a data plane (DP) clock generation unit of a DP subsystem, a frequency level for the DP subsystem;

setting, by a DP power control unit of the DP subsystem, a voltage level for the DP subsystem;

determining, by a DP frequency/voltage selection component of a microcontroller (uC) cluster, a frequency-level adjustment, and a voltage-level adjustment associated with a slot based on a set of inputs, the uC cluster being part of the DP subsystem;

configuring, by the DP frequency/voltage selection component of the uC cluster, the DP clock generation unit with the frequency-level adjustment; and

configuring, by the DP frequency/voltage selection component of the uC cluster, the DP power control unit with the voltage-level adjustment.

16 . The method of claim 15 , wherein the determining, by the DP frequency/voltage selection component of the uC cluster, the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs comprises:

receiving, by a minimum frequency-table adjustment unit, a set of static and semi-static inputs from a DP controller external to the DP subsystem, the DP frequency/voltage selection component including the minimum frequency-table adjustment unit;

generating, by the minimum frequency-table adjustment unit, a minimum frequency adjustment table based on the set of static and semi-static inputs; and

inputting, by the minimum frequency-table adjustment unit, the minimum frequency adjustment table into a minimum frequency-table look-up unit.

17 . The method of claim 16 , wherein the set of static and semi-static inputs includes one or more of a number of component carriers (CCs) associated with a grant, a maximum data throughput per slot and component carrier (CC), a slot duration per CC, an available DP subsystem frequency level, an available DP subsystem voltage level, a logical channel prioritization (LCP) processing rate, or a DP hardware cipher rate.

18 . The method of claim 16 , wherein the determining, by the DP frequency/voltage selection component of the uC cluster, the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs comprises:

receiving, by the minimum frequency-table look-up unit, the minimum frequency adjustment table from the minimum frequency-table adjustment unit, the DP frequency/voltage selection component including the minimum frequency-table look-up unit;

receiving, by the minimum frequency-table look-up unit, a first dynamic input from a physical layer (PHY) controller external to the DP subsystem, a second dynamic input from a logical channel prioritization (LCP) unit, and a third dynamic input from a Layer 2 parsing unit, the DP frequency/voltage selection component including the LCP unit and the Layer 2 parsing unit;

identifying, by the minimum frequency-table look-up unit, the frequency-level adjustment based on the minimum frequency adjustment table and one or more of the first dynamic input, the second dynamic input, or the third dynamic input; and

inputting, by the minimum frequency-table look-up unit, the frequency-level adjustment into a frequency/voltage controller,

wherein the first dynamic input includes a grant size associated with the slot, a grant duration associated with the slot, or a PHY subsystem due time for an uplink packet associated with the slot,

wherein the second dynamic input includes an average-UL packet size associated with the slot, and

wherein the third dynamic input includes an average-DL packet size associated with the slot.

19 . The method of claim 18 , wherein the determining, by the DP frequency/voltage selection component of the uC cluster, the frequency-level adjustment and the voltage-level adjustment associated with the slot based on the set of inputs comprises:

receiving, by the frequency/voltage controller, the frequency-level adjustment from the minimum frequency-table look-up unit;

in response to determining that the frequency-level adjustment meets a frequency-up threshold value or a frequency-down threshold value, identifying a voltage-level adjustment based on the frequency-level adjustment; and

in response to determining that the frequency-level adjustment meets a frequency-up threshold value or a frequency-down threshold value, configure, by the frequency/voltage controller, the DP clock generation unit with the frequency-level adjustment and the DP power control unit with the voltage-level adjustment.

20 . The method of claim 19 , further comprising:

setting, by the DP clock generation unit, a new frequency level for the DP subsystem based on the frequency-level adjustment configured by the frequency/voltage controller, and

setting, by the DP power control unit, a new voltage level for the DP subsystem based on the voltage-level adjustment configured by the frequency/voltage controller.

Assignments (3)

Continuity (1)

References Cited (10)