System and method for triggering a zero-cycle context switch
According to one aspect of the present disclosure, a processor is disclosed. The processor may include a plurality of registers. The plurality of registers may include a first set of registers associated with a regular mode thread. The plurality of registers may also include a second set of registers associated with an interrupt service thread. The processor may also include a processing core. The processing core may be configured to perform first operations associated with the regular mode thread. The processing core may be configured to receive an interrupt service signal associated with the interrupt service thread. In response to the interrupt service signal, the processing core may be configured to implement a zero-cycle context switch to perform second operations associated with the interrupt service thread using the second set of registers.
1 . A processor, comprising:
a plurality of registers comprising:
a first set of registers associated with a regular mode thread; and
a second set of registers associated with an interrupt service thread,
a processing core configured to:
perform first operations associated with the regular mode thread;
receive an interrupt service signal associated with the interrupt service thread; and
in response to the interrupt service signal, implement a zero-cycle context switch to perform second operations associated with the interrupt service thread using the second set of registers,
wherein the processing core is configured to implement the zero-cycle context switch by:
pausing the first operations associated with the regular mode thread; and
maintaining first information associated with the first operations using the first set of registers, and wherein
in response to a completion of the interrupt service thread, the processing core is configured to implement the zero-cycle context switch to resume the first operations associated with the regular mode thread based on the first information maintained by the first set of registers.
2 . The processor of claim 1 , wherein the processing core is further configured to implement the zero-cycle context switch by:
performing second operations associated with the interrupt service thread; and
maintaining, using the second set of registers, second information associated with the interrupt service thread.
3 . The processor of claim 1 , wherein the first set of registers are dedicated to the regular mode thread.
4 . The processor of claim 1 , wherein the second set of registers are dedicated to the interrupt service thread.
5 . The processor of claim 1 , wherein the zero-cycle context switch includes a hardware-based context switch.
6 . The processor of claim 1 , wherein the zero-cycle context switch is implemented without a software-based context switch.
7 . The processor of claim 1 , wherein the plurality of registers includes a general-purpose register (GPR) file.
8 . A system-on-chip (SoC), comprising:
a memory; and
a processor comprising:
a plurality of registers comprising:
a first set of registers associated with a regular mode thread; and
a second set of registers associated with an interrupt service thread,
a processing core configured to:
perform first operations associated with the regular mode thread;
receive an interrupt service signal associated with the interrupt service thread; and
in response to the interrupt service signal, implement a zero-cycle context switch to perform second operations associated with the interrupt service thread using the second set of registers,
wherein the processing core is configured to implement the zero-cycle context switch by:
pausing the first operations associated with the regular mode thread; and
maintaining first information associated with the first operations using the first set of registers, and wherein
in response to a completion of the interrupt service thread, the processing core is configured to implement the zero-cycle context switch to resume the first operations associated with the regular mode thread based on the first information maintained by the first set of registers.
9 . The SoC of claim 8 , wherein the processing core is further configured to implement the zero-cycle context switch by:
performing second operations associated with the interrupt service thread; and
maintaining, using the second set of registers, second information associated with the interrupt service thread.
10 . The SoC of claim 8 , wherein the first set of registers are dedicated to the regular mode thread.
11 . The SoC of claim 10 , wherein the second set of registers are dedicated to the interrupt service thread.
12 . The SoC of claim 8 , wherein the zero-cycle context switch includes a hardware-based context switch.
13 . The SoC of claim 8 , wherein the zero-cycle context switch is implemented without a software-based context switch.
14 . The SoC of claim 8 , wherein the plurality of registers includes a general-purpose register (GPR) file.
15 . A method of performing an interrupt service procedure, comprising:
performing, by a processor, first operations associated with a regular mode thread;
maintaining, by a first set of registers of the processor, first information associated with the regular mode thread;
receiving, by the processor, an interrupt service signal associated with an interrupt service thread; and
in response to the interrupt service signal, implementing, by the processor, a zero-cycle context switch to perform second operations associated with the interrupt service thread using a second set of registers different than the first set of registers,
wherein the first set of registers is associated with the regular mode thread, and the second set of registers is associated with the interrupt service thread, and
wherein the implementing the zero-cycle context switch comprises:
pausing, by the processor, the first operations associated with the regular mode thread; and
maintaining, by the first set of registers of the processor, first information associated with the regular mode thread, and
wherein the implementing the zero-cycle context switch further comprises:
in response to a completion of the interrupt service thread, implementing, by the processor, the zero-cycle context switch to resume the first operations associated with the regular mode thread based on the first information maintained in the first set of registers.
16 . The method of claim 15 , wherein the implementing the zero-cycle context switch further comprises:
performing, by the processor, second operations associated with the interrupt service thread;
maintaining, by the second set of registers of the processor, second information associated with the interrupt service thread.
17 . The method of claim 15 , wherein:
the first set of registers are dedicated to the regular mode thread, and
the second set of registers are dedicated to the interrupt service thread.