Reading method for a memory
The present disclosure relates to a method of reading a word in a memory device, wherein the word is comprised in a first set of words that can be read by the memory device, each word of the first set comprising at least one byte of data, each word being contained in memory cells, the method comprising a pre-charging step during which the first set and at least a second set of words are pre-charged, a first terminal of each cell of the first and second sets being floating during the pre-charging step.
1 . A method of reading a word in a memory device, wherein the word is comprised in a first set of words that can be read by the memory device, wherein each word of the first set comprises at least one byte of data, each word being contained in memory cells, the method comprising a pre-charging step during which the first set and at least a second set of words are pre-charged, a first terminal of each cell of the first and second sets being floating during the pre-charging step.
2 . The method according to claim 1 , wherein the word to be read is designated by an address having first, second and third parts, a partial address comprising the first and second parts indicating the first set, a partial address comprising the first part indicating the first and second sets of words, the method comprising:
a. receiving the first part;
b. pre-charging the first and second sets of words, the first terminal of each of the memory cells corresponding to said words being floating;
c. receiving the second part;
d. maintaining the pre-charge of the first set of words only;
e. reading the first set of words;
f. receiving the third part; and
g. determining the address of the word from the read set.
3 . The method according to claim 2 , wherein the address comprises a line coordinate and a column coordinate.
4 . The method according to claim 3 , wherein the first part comprises at least the line coordinate.
5 . The method according to claim 2 , wherein the first part comprises one or more most significant bits and the third part comprises one or more least significant bits of the address.
6 . The method according to claim 2 , wherein the second part comprises only one bit.
7 . The method according to claim 2 , wherein, during the steps d and e, at reception of each bit of the second part, only the pre-charging of the words whose address starts with a known partial address is maintained.
8 . The method according to claim 2 , wherein the pre-charging comprises applying a first pre-charging voltage value to a second terminal of the pre-charged memory cell.
9 . The method according to claim 8 , wherein, in the step e, the first pre-charging voltage value is no longer maintained at the second terminal of each memory cell and the value of each memory cell is determined by a variation of a voltage or of a current on the second terminal of the pre-charged memory cell with respect to the first pre-charging value.
10 . The method according to claim 1 , wherein the first terminal of each memory cell is coupled to a reference voltage through a transistor that is non-conducting during the pre-charging and conducting during the reading of the word.
11 . The method according to claim 1 , wherein a pre-charging voltage of each word is provided by a sense amplifier.
12 . The method according to claim 11 , wherein the sense amplifier pre-charges at least two words read at step e.
13 . The method according to claim 2 , wherein a sense amplifier pre-charges at least two words read at step e.