ONE-TIME PROGRAMMABLE MEMORY CELL AND METHOD FOR MANAGING THE LOGIC STATE OF THE MEMORY CELL
A memory cell is formed by a PIN diode having three contacts. A breakdown voltage is applied to break down a gate oxide arranged between a region of the PIN diode and a substrate region. The breakdown or non-breakdown state of the gate oxide is determined by applying a read voltage between the anode and the cathode of the diode and determining the value of the corresponding current flowing in the diode.
1 . An integrated memory device, comprising:
a one-time programmable memory cell including a first semiconductor bar having a lower face and an upper face opposite the lower face, a first electrically isolating region located between a first zone of the lower face and a semiconductor region, and a second electrically isolating region thicker than the first electrically isolating region located between a second zone of the lower face and said semiconductor region;
wherein the one-time programmable memory cell has a first logic state in the presence of a non-electrically broken down first electrically isolating region and a second logic state in the presence of an electrically broken down first electrically isolating region;
a first circuit configured to apply a breakdown potential difference between the semiconductor region and the first semiconductor bar so as to break down the first electrically isolating region; and
a second circuit configured to apply a read voltage between two locations of the upper face of the silicon bar and determine the value of the current flowing between the two locations so as to determine the logic state of the one-time programmable memory cell.
2 . The device according to claim 1 , wherein the one-time programmable memory cell includes a first electrically conductive contact, a second electrically conductive contact and a third electrically conductive contact, the first circuit being configured to apply the breakdown potential difference between the third electrically conductive contact and one of the first and second electrically conductive contacts, and the second circuit being configured to apply the read voltage and determine the value of said current between the first electrically conductive contact and the second electrically conductive contact.
3 . The device according to claim 1 , wherein the first bar comprises a PIN diode including an intrinsic polysilicon region between an anode region and a cathode region, the first zone of the lower face of the PIN diode including at least one portion of the lower face of the intrinsic polysilicon region, or of the anode region or of the cathode region, wherein the first circuit is configured to apply the breakdown potential difference between the semiconductor region and the anode region and/or the cathode region, and wherein the second circuit is configured to apply the read voltage between a location of the upper face of the anode region and a location of the upper face of the cathode region.
4 . The device according to claim 3 , wherein the semiconductor region comprises a substrate semiconductor region, the first zone of the lower face of the PIN diode includes at least a portion of the lower face of the anode region and the second zone of the lower face of the PIN diode is located next to the first zone and comprises the rest of the lower face of the PIN diode, the first electrically isolating region comprises an isolating layer, and the second electrically isolating region comprises a shallow isolating trench extending adjacent to said isolating layer under the second zone of the lower face of the PIN diode.
5 . The device according to claim 4 , wherein the substrate semiconductor region has a conductivity type opposite the conductivity type of the anode region.
6 . The device according to claim 3 , wherein the semiconductor region comprises a substrate semiconductor region, the first zone of the lower face of the PIN diode includes at least a portion of the lower face of the cathode region and the second zone of the lower face of the PIN diode is located adjacent to the first zone and comprises the rest of the lower face of the PIN diode, the first electrically isolating region comprises an isolating layer, and the second electrically isolating region comprises a shallow isolating trench extending adjacent to the isolating layer under the second zone of the lower face of the PIN diode.
7 . The device according to claim 6 , wherein the substrate semiconductor region has a conductivity type opposite the conductivity type of the anode region.
8 . The device according to claim 3 , wherein the semiconductor region comprises a substrate semiconductor region, the first zone of the lower face of the PIN diode includes at least a portion of the lower face of the anode region and at least a portion of the lower face of the cathode region, and the second zone of the lower face of the PIN diode is located between said at least one portion of the lower face of the anode region and said at least one portion of the lower face of the cathode region and comprises the rest of the lower face of the PIN diode, the second electrically isolating region comprises a shallow isolating trench extending under the second zone of the lower face of the PIN diode and the first electrically isolating region comprises two isolating layers located respectively on either side of the shallow isolating trench.
9 . The device according to claim 8 , wherein the substrate semiconductor region has a conductivity type opposite the conductivity type of the anode region.
10 . The device according to claim 3 , wherein the semiconductor region comprises a second semiconductor bar located between the lower face of the PIN diode and a third electrically isolating region, the first zone of the lower face of the PIN diode includes at least a portion of the lower face of the intrinsic polysilicon region and the second zone of the lower face of the PIN diode is located on either side of the first zone, the first electrically isolating region includes a first isolating layer and the second electrically isolating region includes a second isolating layer thicker than the first isolating layer.
11 . The device according to claim 10 , wherein the third electrically isolating region includes a shallow isolating trench.
12 . The device according to claim 10 , wherein the second bar has a conductivity type opposite that of the anode region.
13 . The device according to claim 3 , wherein the first zone of the lower face of the PIN diode includes at least a portion of the lower face of the intrinsic polysilicon region and the second zone of the lower face of the PIN diode is located on either side of the first zone, the first electrically isolating region includes a first isolating layer and the second electrically isolating region includes a second isolating layer thicker than the first isolating layer, the semiconductor region includes a semiconductor trench contacting the first isolating layer and extending through a fourth electrically isolating region.
14 . The device according to claim 13 , wherein the fourth electrically isolating region includes a shallow trench.
15 . The device according to claim 13 , wherein the semiconductor trench has a conductivity type opposite the conductivity type of the anode region.
16 . The device according to claim 1 , wherein the first semiconductor bar has a single conductivity type.
17 . The device according to claim 16 , wherein the single conductivity type of the first semiconductor bar is opposite the conductivity type of the semiconductor region.
18 . A method for managing the logic state of a one-time programmable memory cell, the one-time programmable memory cell including a first semiconductor bar having a lower face and an upper face opposite the lower face, a first electrically isolating region located between a first zone of the lower face and a semiconductor region, a second electrically isolating region thicker than the first electrically isolating region located between a second zone of the lower face and said semiconductor region, the method comprising:
wherein the one-time programmable memory cell has a first logic state in the presence of a non-electrically broken down first electrically isolating region;
wherein the one-time programmable memory cell has a second logic state in the presence of an electrically broken down first electrically isolating region; and
breaking down the first electrically isolating region by applying a breakdown potential difference between the semiconductor region and the semiconductor bar.
19 . The method according to claim 18 , wherein the first bar comprising a PIN diode including an intrinsic polysilicon region between an anode region and a cathode region, the first zone of the lower face of the PIN diode including at least a portion of the lower face of the intrinsic polysilicon region, or of the anode region and/or of the cathode region, the breakdown potential difference is applied between the semiconductor region and the anode region and/or the cathode region, and the read voltage is applied between a location of the upper face of the anode region and a location of the upper face of the cathode region.
20 . A method for managing the logic state of a one-time programmable memory cell, the one-time programmable memory cell including a first semiconductor bar having a lower face and an upper face opposite the lower face, a first electrically isolating region located between a first zone of the lower face and a semiconductor region, a second electrically isolating region thicker than the first electrically isolating region located between a second zone of the lower face and said semiconductor region, the method comprising:
wherein the one-time programmable memory cell has a first logic state in the presence of a non-electrically broken down first electrically isolating region;
wherein the one-time programmable memory cell has a second logic state in the presence of an electrically broken down first electrically isolating region; and
determining the logic state of the memory cell by applying a read voltage between two locations of the upper face of the silicon bar and determining the value of the current flowing between the two locations.
21 . The method according to claim 20 , wherein the first bar comprising a PIN diode including an intrinsic polysilicon region between an anode region and a cathode region, the first zone of the lower face of the PIN diode including at least a portion of the lower face of the intrinsic polysilicon region, or of the anode region and/or of the cathode region, the breakdown potential difference is applied between the semiconductor region and the anode region and/or the cathode region, and the read voltage is applied between a location of the upper face of the anode region and a location of the upper face of the cathode region.