Granted Patent B2

US 12,475,941 · App. 18/587,207 · Granted Nov 18, 2025

Inventor: Richard C. Murphy (Boise, ID)

G11C11/4091G11C7/08G11C7/1006G11C11/4076G06F3/0611G06F3/0659G06F3/068G11C7/1048G11C11/4093G11C11/4096

Abstract

Claims (56)

1 . An apparatus, comprising:

a logic component; and

a plurality of memory components coupled with the logic component via one or more through silicon vias (TSVs);

wherein each respective memory component of the plurality of memory components comprises:

a plurality of timing circuitry;

a plurality of banks each comprising a respective array of memory cells, wherein a respective timing circuit of the plurality of timing circuitry is coupled with a respective bank of the plurality of banks; and

circuitry comprising sensing circuitry and a compute component of the respective memory component, the circuitry coupled to the array and configured to perform one or more logical operations using data stored in the array of memory cells;

wherein the logic component comprises:

a first control logic coupled to a first group of partitioned banks of the plurality of memory components, wherein at least two partitioned banks of the first group are on different memory components;

a second control logic coupled to a second group of partitioned banks of the plurality of memory components; and

switching circuitry configured to:

route memory array requests received from a host between the first control logic and the second control logic; and

route processing-in-memory (PIM) requests received from the host between the first control logic and the second control logic to perform the one or more logical operations, wherein routing the memory array requests and the PIM requests is based at least in part on a scheduling policy.

2 . The apparatus of claim 1 , wherein each respective memory component of the plurality of memory components further comprises a sequencer, the sequencer configured to execute microcode function calls to cause the circuitry to perform the one or more logical operations.

3 . The apparatus of claim 1 , wherein the one or more logical operations includes an addition operation or multiplication operation, or both.

4 . The apparatus of claim 1 , wherein each respective memory component of the plurality of memory components further comprises one or more registers.

5 . The apparatus of claim 4 , wherein the one or more registers correspond to extend row address (XRA) registers.

6 . The apparatus of claim 1 , wherein the first control logic is configured to access the first group of partitioned banks in parallel.

7 . A system, comprising:

a logic component; and

a plurality of memory components coupled with the logic component;

wherein each respective memory component of the plurality of memory components comprises:

a plurality of timing circuitry;

a plurality of a banks each comprising a respective array of memory cells, wherein a respective timing circuit of the plurality of timing circuitry is coupled with a respective bank of the plurality of banks;

circuitry comprising sensing circuitry and a compute component of the respective memory component, the circuitry coupled to the array and configured to perform one or more logical operations using data stored in the array of memory cells; and

a sequencer configured to cause the circuitry to perform the one or more logical operations;

wherein the logic component comprises:

a first control logic coupled to a first group of partitioned banks of the plurality of memory components; and

a second control logic coupled to a second group of partitioned banks of the plurality of memory components; and

switching circuitry configured to:

route memory array requests received from a host between the first control logic and the second control logic; and

route processing-in-memory (PIM) requests received from the host between the first control logic and the second control logic to perform the one or more logical operations, wherein routing the memory array requests and the PIM requests is based at least in part on a scheduling policy.

8 . The system of claim 7 , wherein the circuitry of each respective memory component is configured to perform logical Boolean operations.

9 . The system of claim 7 , wherein the sequencer is configured to execute PIM instructions to cause the circuitry to perform the one or more logical operations.

10 . The system of claim 7 , wherein the one or more logical operations correspond to PIM operations.

11 . The system of claim 7 , wherein the one or more logical operations includes an addition operation or multiplication operation, or both.

12 . The system of claim 7 , wherein the plurality of memory components are coupled with the logic component via one or more through silicon vias (TSVs).

13 . An apparatus, comprising:

a logic component; and

a plurality of memory components coupled with the logic component;

wherein a respective memory component of the plurality of memory components comprises:

a plurality of timing circuitry; and

a plurality of banks each comprising a respective array of memory cells, wherein a respective timing circuit of the plurality of timing circuitry is coupled with a respective bank of the plurality of banks;

wherein the logic component comprises:

a first control logic coupled to one or more first portions of the plurality of memory components, the first control logic configured to operate on a reduced instruction set computer (RISC) type instruction and to further cause performance of the one or more logical operations using data stored in a respective array of memory cells and corresponding to processing in memory (PIM) operations;

a second control logic coupled to one or more second portions of the plurality of memory components, the second control logic configured to operate on a RISC type instruction and to further cause performance of one or more logical operations using data stored in a respective array of memory cells and corresponding to PIM operations; and

switching circuitry configured to:

route memory array requests received from a host between the first control logic and the second control logic; and

route PIM requests received from the host between the first control logic and the second control logic to perform the one or more logical operations, wherein routing the memory array requests and the PIM requests is based at least in part on a scheduling policy.

14 . The apparatus of claim 13 , wherein the logic component further comprises a sequencer, the sequencer configured to execute microcode function calls to cause performance of the one or more logical operations.

15 . The apparatus of claim 13 , wherein the first control logic or the second control logic is further configured to fetch and decode instructions to cause performance of the one or more logical operations corresponding to PIM operations.

16 . The apparatus of claim 13 , wherein the first control logic or the second control logic, or both, is further configured to operate on one or more 32-bit length RISC instructions.

17 . The apparatus of claim 13 , wherein the respective memory component of the plurality of memory components further comprises one or more registers that are mapped to a plurality of locations where instructions executable by the first control logic or second control logic are stored.

18 . The apparatus of claim 13 , wherein the first control logic is configured to access the one or more first portions of the plurality of memory components in parallel.

19 . The apparatus of claim 13 , wherein the second control logic is configured to access the one or more second portions of the plurality of memory components in parallel.

20 . The apparatus of claim 13 , wherein the one or more first portions and the one or more second portions of the plurality of memory components are accessible in parallel respectively by the first and second control logics.

Assignments (1)

Continuity (6)

References Cited (398)