Integrated circuit comprising a test circuit, related method and computer-program product
An integrated circuit includes a sequential logic circuit and a circuit configured to change operation as a function of state output signals provided by state flip-flops of the sequential logic circuit. With a test mode signal asserted, a test circuit writes and reads the content of the state flip-flops in order to test the operation of the sequential logic circuit. A processing system includes at least one storage circuit interposed between the circuit and a respective state output signal. Each storage circuit receives the respective state output signal and provides a modified state signal to the circuit. When the test mode signal is de-asserted, the storage circuit provides the received state output signal in a transparent manner to the circuit and stores the received state output signal to a storage element. When the test mode signal is asserted, the storage circuit provides the stored state output signal to the circuit.
1 . An integrated circuit, comprising:
a sequential logic circuit comprising:
a plurality of state flip-flops that provide a state signal of said sequential logic circuit, wherein each state flip-flop is configured to generate a state output signal by storing an input signal in response to a clock signal; and
a next-state combinational logic circuit configured to generate said input signals for said plurality of state flip-flops as a function of said state output signals of said plurality of state flip-flops and at least one input signal;
a circuit configured to change operation as a function of a subset of the state output signals provided by said plurality of state flip-flops;
a test circuit configured, when a test mode signal is asserted, to write and read the content of said plurality of state flip-flops in order to test the operation of said sequential logic circuit; and
a plurality of storage circuits, wherein each storage circuit is interposed between said circuit and a respective state output signal of said subset of state output signals, wherein each storage circuit is configured to receive the respective state output signal and provide a modified state signal to said circuit, and wherein each storage circuit:
provides, when said test mode signal is de-asserted, the received state output signal in a transparent manner as the modified state signal to said circuit and stores the received state output signal to a storage element of said storage circuit as a stored state output signal; and
inhibits, when said test mode signal is asserted, storage of the received state output signal to said storage element of said storage circuit and provides the stored state output signal as the modified state signal to said circuit;
wherein a number of said storage circuits is smaller than a number of state flip-flops in said plurality of state flip-flops.
2 . The integrated circuit according to claim 1 , wherein said storage circuit comprises:
a storage flip-flop configured to store, in response to said clock signal, the respective received state output signal when said test mode signal is de-asserted.
3 . The integrated circuit according to claim 2 , wherein said storage circuit comprises:
a first multiplexer configured to generate an input signal of the respective storage flip-flop by selecting:
the received state output signal when said test mode signal is de-asserted, and
the output signal of said storage flip-flop when said test mode signal is asserted; and
a second multiplexer configured to generate the modified state signal by selecting:
the received state output signal when said test mode signal is de-asserted, and
the output signal of said storage flip-flop when said test mode signal is asserted.
4 . The integrated circuit according to claim 1 , wherein said test circuit comprises a scan-chain, wherein each state flip-flop of said plurality of state flip-flops forms part of a respective scan element, wherein:
a first scan element is configured to provide a serial input signal to the input of the respective state flip-flop when a scan mode enable signal is asserted;
following scan elements are configured to provide the state output signal of the state flip-flop of a previous scan-element to the input of the respective state flip-flop when a scan mode enable signal is asserted; and
wherein the state output signal of the state flip-flop of a last scan-element corresponds to a serial output signal.
5 . The integrated circuit according to claim 4 , wherein said test circuit comprises a test port, configured to:
assert said scan mode enable signal;
sequentially apply data to said serial input signal in order to load data into said plurality of state flip-flops;
de-assert said scan mode enable signal, whereby said sequential logic circuit updates the content of said plurality of state flip-flops;
assert said scan mode enable signal; and
sequentially read said serial output signal in order to read the content of said plurality of state flip-flops.
6 . The integrated circuit according to claim 5 , wherein said test port is configured to generate the clock signal for said plurality of state flip-flops when said test mode signal is asserted.
7 . The integrated circuit according to claim 5 , wherein said test port is further configured to control a scan mode enable signal and a test clock signal independently to facilitate different testing modes.
8 . The integrated circuit according to claim 4 , wherein said scan-chain further comprises a plurality of intermediate scan elements between said first scan element and said last scan-element, wherein each intermediate scan element is configured to pass data serially from a previous scan element to a next scan element in said scan-chain.
9 . The integrated circuit according to claim 1 , wherein individual storage circuits within said processing system are selectively enabled and disabled based on power management requirements of said circuit.
10 . The integrated circuit according to claim 1 , wherein said storage circuit further comprises a reset terminal configured to reset said storage element to a predetermined state in response to a reset signal.
11 . The integrated circuit according to claim 1 , wherein said next-state combinational logic circuit is configured to generate said input signals based on external input signals received at input pads of said integrated circuit.
12 . The integrated circuit according to claim 1 , wherein said storage element comprises a latch circuit configured to maintain said stored state output signal during said test mode.
13 . The integrated circuit according to claim 1 , wherein said circuit configured to change operation comprises a digital circuit that modifies its logic function based on said modified state signals.
14 . The integrated circuit according to claim 1 , wherein said test circuit is further configured to generate boundary scan test patterns for testing interconnections between said integrated circuit and external components.
15 . An integrated circuit, comprising:
a sequential logic circuit comprising:
a plurality of state flip-flops that provide a state signal of said sequential logic circuit, wherein each state flip-flop is configured to generate a state output signal by storing an input signal in response to a clock signal; and
a next-state combinational logic circuit configured to generate said input signals for said plurality of state flip-flops as a function of said state output signals of said plurality of state flip-flops and at least one input signal;
a circuit configured to change operation as a function of a subset of the state output signals provided by said plurality of state flip-flops;
a test circuit configured, when a test mode signal is asserted, to write and read the content of said plurality of state flip-flops in order to test the operation of said sequential logic circuit; and
a storage circuit interposed between said circuit and a respective state output signal of said subset of state output signals, wherein each storage circuit is configured to receive the respective state output signal and provide a modified state signal to said circuit, and wherein each storage circuit:
provides, when said test mode signal is de-asserted, the received state output signal in a transparent manner as the modified state signal to said circuit and stores the received state output signal to a storage element of said storage circuit as a stored state output signal; and
inhibits, when said test mode signal is asserted, storage of the received state output signal to said storage element of said storage circuit and provides the stored state output signal as the modified state signal to said circuit;
wherein said circuit comprises an analog circuit configured to change operation as a function of said modified state signals.
16 . The integrated circuit according to claim 15 , wherein said analog circuit comprises at least one of: a power supply, a current or voltage regulator, and a ground switch.
17 . The integrated circuit according to claim 15 , wherein said storage circuit comprises:
a storage flip-flop configured to store, in response to said clock signal, the respective received state output signal when said test mode signal is de-asserted.
18 . The integrated circuit according to claim 17 , wherein said storage circuit comprises:
a first multiplexer configured to generate an input signal of the respective storage flip-flop by selecting:
the received state output signal when said test mode signal is de-asserted, and
the output signal of said storage flip-flop when said test mode signal is asserted; and
a second multiplexer configured to generate the modified state signal by selecting:
the received state output signal when said test mode signal is de-asserted, and
the output signal of said storage flip-flop when said test mode signal is asserted.
19 . The integrated circuit according to claim 15 , wherein said test circuit comprises a scan-chain, wherein each state flip-flop of said plurality of state flip-flops forms part of a respective scan element, wherein:
a first scan element is configured to provide a serial input signal to the input of the respective state flip-flop when a scan mode enable signal is asserted;
following scan elements are configured to provide the state output signal of the state flip-flop of a previous scan-element to the input of the respective state flip-flop when a scan mode enable signal is asserted; and
wherein the state output signal of the state flip-flop of a last scan-element corresponds to a serial output signal.
20 . The integrated circuit according to claim 19 , wherein said test circuit comprises a test port, configured to:
assert said scan mode enable signal;
sequentially apply data to said serial input signal in order to load data into said plurality of state flip-flops;
de-assert said scan mode enable signal, whereby said sequential logic circuit updates the content of said plurality of state flip-flops;
assert said scan mode enable signal; and
sequentially read said serial output signal in order to read the content of said plurality of state flip-flops.
21 . The integrated circuit according to claim 20 , wherein said test port is configured to generate the clock signal for said plurality of state flip-flops when said test mode signal is asserted.
22 . The integrated circuit according to claim 20 , wherein said test port is further configured to control a scan mode enable signal and a test clock signal independently to facilitate different testing modes.
23 . The integrated circuit according to claim 19 , wherein said scan-chain further comprises a plurality of intermediate scan elements between said first scan element and said last scan-element, wherein each intermediate scan element is configured to pass data serially from a previous scan element to a next scan element in said scan-chain.
24 . The integrated circuit according to claim 15 , wherein said test circuit is further configured to generate boundary scan test patterns for testing interconnections between said integrated circuit and external components.