HEMT DEVICE HAVING A REDUCED GATE LEAKAGE AND MANUFACTURING PROCESS THEREOF

1 . An HEMT device comprising:

a semiconductor body having a semiconductive heterostructure;

a control region, comprising a semiconductor material, on the semiconductor body, the control region having a top surface and a plurality of lateral sides;

a control terminal, of conductive material, extending on and in contact with the top surface of the control region;

a passivation layer of non-conductive material, extending on the semiconductor body, partially on the top surface of the control region and on the plurality of lateral sides of the control region, the passivation layer arranged laterally and at a distance from the control terminal; and

a plurality of spacer regions of non-conductive material, extending between the control terminal and the passivation layer, the passivation layer not overlapping the plurality of spacer regions.

2 . The HEMT device according to claim 1 , wherein the plurality of spacer regions is thicker than the passivation layer.

3 . The HEMT device according to claim 2 , wherein the control terminal comprises a narrow portion, extending between the plurality of spacer regions, and an upper portion, extending on the plurality of spacer regions.

4 . The HEMT device according to claim 2 , further comprising an insulating structure extending on the passivation layer, wherein a control opening extends in the insulating structure and through the passivation layer and accommodates, at least partially, the control terminal and the plurality of spacer regions, the control opening having lateral sides, the plurality of spacer regions extending on the plurality of lateral sides of the control opening.

5 . The HEMT device according to claim 2 , wherein the insulating structure comprises:

a first insulating layer extending on passivation layer, and

a second insulating layer extending on the first insulating layer, and

wherein the control opening extends through the first insulating layer and the passivation layer and accommodates the plurality of spacer regions and, at least in part, the control terminal, the second insulating layer extending on the control terminal.

6 . The HEMT device according to claim 4 , wherein the insulating structure comprises:

a first insulating layer extending on passivation layer, and

a second insulating layer extending on the first insulating layer, and

wherein the control opening extends throughout the first and the second insulating layers and the passivation layer and accommodates the plurality of spacer regions and the control terminal.

7 . The device of claim 6 , further comprising a field plate, the field plate being between the first insulating layer and the second insulating layer.

8 . The device of claim 7 , further comprising a first current conducting terminal and a second current conducting terminal, the first and second current conducting terminal being partially between the first insulating layer and the second insulating layer, the first and the second current conducting terminal being in contact with the semiconductor body.

9 . The device of claim 7 , further comprising a first current conducting terminal and a second current conducting terminal, the first and second current conducting terminal being partially above the first insulating layer and the second insulating layer, the first and the second current conducting terminal being in contact with the semiconductor body, the first current conducting terminal being partially above the control terminal and the field plate.

10 . The HEMT device according to claim 6 , wherein the insulating structure and the plurality of spacer regions are of different, selectively etchable materials.

11 . The HEMT device according to claim 10 , wherein the insulating structure is of silicon oxide and the plurality of spacer regions are of silicon nitride.

12 . The HEMT device according to claim 11 , wherein the control region comprises a channel modulating region and an interlayer region overlying the channel modulating region.

13 . A process for manufacturing an HEMT device, the process comprising:

on a semiconductor body having a semiconductive heterostructure, forming a control region, the control region including a semiconductor material and on the semiconductor body, the control region having a top surface and lateral sides;

forming a passivation layer of non-conductive material, on the semiconductor body, partially on the top surface of the control region and on the lateral sides of the control region;

forming spacer regions, of non-conductive material, extending between the control terminal and the passivation layer; and

forming a control terminal, of conductive material, on and in contact with the top surface of the control region, laterally and at a distance from the passivation layer.

14 . The process according to claim 13 , wherein the spacer regions are taller than the passivation layer.

15 . The process according to claim 14 , wherein:

forming a passivation layer and forming spacer regions includes:

forming a portion of the passivation layer covering the top surface of the control region;

forming a first insulating layer on the passivation layer;

forming a control opening in the first insulating layer, including selectively removing the portion of the passivation layer; and

forming the spacer regions on lateral sides of the control opening; and

forming a control terminal including a portion of the control terminal in the control opening, between and on the spacer regions.

16 . The process according to claim 15 ,

wherein forming the spacer regions comprises:

forming a sacrificial layer on the first insulating layer and in the control opening; and

removing the sacrificial layer from the first insulating layer and in the control opening, except of at lateral sides of the control opening.

17 . The process according to claim 16 , further comprising:

after forming a control terminal, forming a second insulating layer;

forming a first and a second current conduction opening through the first and second insulating layers and the passivation layer on a first and, respectively, a second side of the control region; and

forming a first current conducting terminal extending, at least partially, in the first current conduction opening and a second current conducting terminal extending, at least partially, in the second current conduction opening, the first and second current conducting terminals being in contact with the semiconductor body.

18 . The process according to claim 16 , further comprising:

after forming the first insulating layer, forming a first and a second current conduction opening through the first insulating layer and the passivation layer, on a first and, respectively, a second side of the control region;

forming a first current conducting terminal extending, at least partially, in the first current conduction opening and a second current conducting terminal extending, at least partially, in the second current conduction opening, the first and second current conducting terminals being in contact with the semiconductor body; and

forming a second insulating layer, wherein forming a control opening in the first insulating layer further includes:

forming the control opening in the second insulating layer, the control opening extending through both the first and the second insulating layers.

19 . A device, comprising:

a semiconductor heterostructure;

a control region on the heterostructure, the control region having a first surface and a plurality of sides;

a terminal on and in contact with the first surface of the control region;

a passivation layer on the heterostructure, on the first surface of the control region and on the plurality of sides of the control region, the passivation layer having a second surface that is transverse to the first surface; and

a plurality of non-conductive spacer regions between the terminal and the passivation layer, the second surface of the passivation layer in contact with the plurality of spacer regions.

20 . The device of claim 19 , further comprising:

a first insulating layer on the passivation layer;

a second insulating layer on the first insulating layer, the first insulating layer and the second insulating layer in contact with the plurality of spacer regions at the second surface; and

a field plate between the first and the second insulating layers.