Memory command verification
View Patent ↗Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.
1. A method, comprising:
receiving a series of commands at a memory device, wherein the series of commands comprises a command;
determining an error associated with the command;
accessing respective locations of a memory array of the memory device in response to the series of commands, wherein accessing at least one of the respective locations occurs concurrently with determining the error; and
transmitting signaling to a host device that indicates the error associated with the command.
2. A method, comprising:
receiving a command at a memory device, wherein the command is associated with a first location of a memory array;
determining a second location of the memory array that is accessed based on receiving the command;
determining an error associated with the command based at least in part on comparing the first location and the second location; and
transmitting signaling to a host device that indicates the error associated with the command.
3. The method of claim 2 , further comprising:
decoding the command, wherein the second location is accessed based at least in part on the decoding the command.
4. The method of claim 2 , further comprising:
determining, based at least in part on the command, an instruction for access of the memory array; and
determining the error based at least in part on comparing a type of access for the second location to the instruction.
5. The method of claim 2 , further comprising:
determining a matrix (MAT) or a sub-array of the memory array corresponding to the second location of the memory array; and
determining the error associated with the command based at least in part on the MAT or the sub-array of the memory array.
6. The method of claim 1 , wherein the memory device comprises a dynamic random access memory (DRAM), and wherein the command is received at the DRAM.
7. A memory device, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and operable to execute the code to cause the memory device to:
receive a series of commands at the memory device, wherein the series of commands comprises a command;
determine an error associated with the command;
access respective locations of a memory array of the memory device in response to the series of commands, wherein accessing at least one of the respective locations occurs concurrently with determining the error; and
transmit signaling to a host device that indicates the error associated with the command.
8. A memory device, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and operable to execute the code to cause the memory device to:
receive a command at the memory device, wherein the command is associated with a first location of a memory array;
determine a second location of the memory array that is accessed based on receiving the command;
determine an error associated with the command based at least in part on comparing the first location and the second location; and
transmit signaling to a host device that indicates the error associated with the command.
9. The memory device of claim 8 , wherein the one or more processors are individually or collectively further operable to execute the code to cause the memory device to:
decode the command, wherein the second location is accessed based at least in part on the decoding the command.
10. The memory device of claim 8 , wherein the one or more processors are individually or collectively further operable to execute the code to cause the memory device to:
determine, based at least in part on the command, an instruction for access of the memory array; and
determine the error based at least in part on comparing a type of access for the second location to the instruction.
11. The memory device of claim 8 , wherein the one or more processors are individually or collectively further operable to execute the code to cause the memory device to:
determine a matrix (MAT) or a sub-array of the memory array corresponding to the second location of the memory array; and
determine the error associated with the command based at least in part on the MAT or the sub-array of the memory array.
12. The memory device of claim 8 , wherein the memory device comprises a dynamic random access memory (DRAM), and wherein the command is received at the DRAM.
13. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
receive a series of commands at a memory device, wherein the series of commands comprises a command;
determine an error associated with the command;
access respective locations of a memory array of the memory device in response to the series of commands, wherein accessing at least one of the respective locations occurs concurrently with determining the error; and
transmit signaling to a host device that indicates the error associated with the command.
14. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
receive a command at a memory device, wherein the command is associated with a first location of a memory array;
determine a second location of the memory array that is accessed based on receiving the command;
determine an error associated with the command based at least in part on comparing the first location and the second location; and
transmit signaling to a host device that indicates the error associated with the command.
15. The non-transitory computer-readable medium of claim 14 , wherein the instructions are further executable by the one or more processors to:
decode the command, wherein the second location is accessed based at least in part on the decoding the command.
16. The non-transitory computer-readable medium of claim 14 , wherein the instructions are further executable by the one or more processors to:
determine, based at least in part on the command, an instruction for access of the memory array; and
determine the error based at least in part on comparing a type of access for the second location to the instruction.
17. The non-transitory computer-readable medium of claim 14 , wherein the instructions are further executable by the one or more processors to:
determine a matrix (MAT) or a sub-array of the memory array corresponding to the second location of the memory array; and
determine the error associated with the command based at least in part on the MAT or the sub-array of the memory array.