IP Library Granted Patent US 12,587,099
Granted Patent B2
US 12,587,099 · App. 18/594,776 · Granted Mar 24, 2026

Coil short circuit protection in DC-DC converters

Inventors: Alessandro Bertolini (Vermiglio, IT); Alessandro Gasparini (Cusano Milanino, IT)
Assignee: STMicroeIectronics International N.V.
H02M3/1588H02H7/1213H02M1/0009H02M1/32H02M1/36H02M3/1582
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Quick Facts
Patent No.
US 12,587,099
App. No.
18/594,776
Granted
Mar 24, 2026
Kind
B2
Abstract

Circuitry for detecting a short across an inductor of a DC-DC converter includes a decoupling-circuit coupled between an inductor-terminal and an intermediate-node that, when activated, generates a detection-voltage (representative of voltage at the inductor-terminal) at the intermediate-node. A logic-circuit has an input coupled to the intermediate-node and an output generating a detection-signal. The detection-signal is asserted when the detection-voltage is closer to an input-voltage to the DC-DC converter than ground but is deasserted when the detection-voltage is closer to ground. Control-circuitry, at the beginning of a high-side conduction-phase, activates the decoupling-circuit and delays for a delay-period. After expiration of the delay-period and in response to the detection-signal being asserted, the control-circuitry completes the high-side conduction-phase. After expiration of the delay period and when the detection-signal is deasserted, the control-circuitry ceases the high-side conduction-phase of the DC-DC converter without completing the high-side conduction-phase and prevent beginning of a low-side conduction-phase.

Claims (40)

1 . An inductor short detection circuit for detecting a short across an inductor of a DC-DC converter, comprising:

a decoupling circuit coupled between a terminal of the inductor and an intermediate node, wherein the decoupling circuit is configured to, when activated, generate a detection voltage at the intermediate node, the detection voltage being representative of a voltage at the terminal of the inductor;

a logic circuit having an input coupled to the intermediate node and an output at which a detection signal is produced, the detection signal being asserted by the logic circuit in response to the detection voltage being closer to an input voltage to the DC-DC converter than to ground but being deasserted by the logic circuit in response to the detection voltage being closer to ground than to the input voltage to the DC-DC converter; and

control circuitry configured to, in response to beginning of a high-side conduction phase of the DC-DC converter:

activate the decoupling circuit;

delay for a delay period;

after expiration of the delay period and in response to the detection signal being asserted, complete the high-side conduction phase of the DC-DC converter; and

after expiration of the delay period and in response to the detection signal being deasserted, cease the high-side conduction phase of the DC-DC converter without completing the high-side conduction phase and prevent beginning of a low-side conduction phase of the DC-DC converter.

2 . The inductor short detection circuit of claim 1 , wherein the decoupling circuit comprises a decoupling transistor connected between the terminal of the inductor and the intermediate node, wherein the decoupling transistor is configured to be turned on in response to the beginning of a high-side conduction phase of the DC-DC converter.

3 . The inductor short detection circuit of claim 1 , wherein the logic circuit comprises an inverter having an input coupled to the intermediate node and an output at which the detection signal is produced.

4 . The inductor short detection circuit of claim 3 , wherein the inverter is powered between the input voltage to the DC-DC converter and a clamp voltage.

5 . The inductor short detection circuit of claim 4 , wherein the logic circuit comprises an additional inverter having an input connected to the intermediate node and an output connected to the input of the inverter.

6 . The inductor short detection circuit of claim 5 , wherein the additional inverter is powered between the input voltage to the DC-DC converter and the clamp voltage.

7 . The inductor short detection circuit of claim 6 ,

wherein the decoupling circuit comprises a decoupling transistor connected between the terminal of the inductor and the intermediate node; and

further comprising a control inverter configured to turn on the decoupling transistor in response to assertion of a high-side control signal for a high-side transistor of the DC-DC converter.

8 . The inductor short detection circuit of claim 7 , wherein the control inverter is powered between the input voltage to the DC-DC converter and the clamp voltage.

9 . The inductor short detection circuit of claim 8 , further comprising a clamp voltage generation circuit, the clamp voltage generation circuit comprising:

a first transistor having a first conduction terminal coupled to the input voltage to the DC-DC converter through a first diode, a second conduction terminal connected to a current sink and to a control terminal of the first transistor; and

a second transistor having a first conduction terminal coupled to the input voltage to the DC-DC converter through a first resistor, a second conduction terminal coupled to ground, and a control terminal coupled to the control terminal and second conduction terminal of the first transistor;

wherein the clamp voltage is formed at a tap between the first conduction terminal of the second transistor and the first resistor.

10 . The inductor short detection circuit of claim 1 , further comprising a counter circuit configured to be used by the control circuitry to delay for the delay period.

11 . The inductor short detection circuit of claim 10 , wherein the counter circuit comprises:

a timing capacitor connected between a timing node and ground;

a current source configured to source a charging current to the timing node;

a reset transistor configured to turn off to permit charging of the timing capacitor by the charging current in response to beginning of the high-side conduction phase of the DC-DC converter; and

a comparator configured to indicate expiration of the delay period in response to a voltage at the timing node becoming at least equal to a reference voltage.

12 . A method for detecting a short circuit across an inductor of a DC-DC converter, the method comprising:

in response to beginning of a high-side conduction phase of the DC-DC converter, generating a detection voltage representative of a voltage at a terminal of the inductor;

delaying for a delay period;

asserting a detection signal based upon the detection voltage being closer to an input voltage to the DC-DC converter than to ground, but deasserting the detection signal based upon the detection voltage being close to ground than to the input voltage to the DC-DC converter;

after expiration of the delay period and in response to the detection signal being asserted, completing the high-side conduction phase of the DC-DC converter; and

after expiration of the delay period and in response to the detection signal being deasserted, ceasing the high-side conduction phase of the DC-DC converter without completing the high-side conduction phase and preventing beginning of a low-side conduction phase of the DC-DC converter.

13 . The method of claim 12 , further comprising:

in response to beginning the high-side conduction phase, activating a decoupling circuit connected between the terminal of the inductor and an intermediate node to generate the detection voltage at the intermediate node; and

upon expiration of the delay period, sensing the detection voltage using a logic circuit that asserts or deasserts the detection signal based thereupon.

14 . The method of claim 13 , wherein sensing the detection voltage using the logic circuit comprises:

powering an inverter between the input voltage to the DC-DC converter and a clamp voltage; and

sensing the detection voltage using the inverter, which has its input coupled to the detection voltage.

15 . The method of claim 12 , wherein delaying for a given delay period is performed by charging a timing capacitor until a voltage across the timing capacitor becomes equal to a reference voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068434/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2024
From: BERTOLINI, ALESSANDRO; GASPARINI, ALESSANDRO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 066646/0566 →
Continuity (1)
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