MULTILAYER CERAMIC CAPACITORS (MLCC) ARRAY AND INTEGRATION WITH ACTIVE DEVICES
Packages and methods for fabricating a module with reduced area, including forming a resin-based substrate by forming a resin on a plurality of multilayer ceramic capacitors (MLCCs). Packages and methods for fabricating a module with reduced area include forming a MLCC-based substrate by forming a resin on a plurality of MLCCs, wherein each MLCC of the plurality of MLCCs directly contacts another MLCC.
1 . A method for fabricating a module with reduced area, comprising:
forming a resin-based substrate by:
attaching a plurality of multilayer ceramic capacitors (MLCCs) to a base sheet;
molding resin around the base sheet; and
performing one of: (a) removing the base sheet and adding a redistribution layer (RDL) at surfaces of the plurality of MLCCs from which the base sheet is removed; or (b) grinding the molded resin to surfaces of the plurality of MLCCs opposite to surfaces of the plurality of MLCCs facing the base sheet;
forming the RDL in an insulating layer on the resin-based substrate; and
coupling an integrated circuit (IC) to the resin-based substrate.
2 . The method of claim 1 , wherein the resin comprises an epoxy.
3 . The method of claim 1 , wherein the insulating layer comprises a polyimide or an oxide.
4 . The method of claim 1 , wherein at least two MLCCs of the plurality of MLCCs are electrically coupled to each other.
5 . The method of claim 1 , wherein one of the MLCCs has a voltage rating that is different from that of another of the MLCCs.
6 . The method of claim 1 , further comprising forming at least one pad on the RDL.
7 . The method of claim 6 , wherein the IC is coupled to the resin-based substrate by at least one solder bump or copper pillar on the at least one pad.
8 . The method of claim 6 , wherein the RDL comprises a first passivation layer and the at least one pad is on the first passivation layer.
9 . The method of claim 8 , wherein the RDL comprises a second passivation layer and the at least one pad is between the first passivation layer and the second passivation layer.
10 . The method of claim 1 , wherein the IC is electrically coupled to at least one MLCC of the plurality of MLCCs.
11 . The method of claim 1 , wherein coupling the IC to the resin-based substrate comprises thermo-compression bonding.
12 . The method of claim 1 , wherein coupling the IC to the resin-based substrate comprises hybrid bonding.
13 . The method of claim 12 , wherein the hybrid bonding is between at least one plug of the IC and at least one plug embedded in the insulating layer.
14 . The method of claim 1 , wherein coupling the IC to the resin-based substrate comprises connecting the IC to the resin-based substrate with a wire.
15 . The method of claim 1 , further comprising grinding the IC to 50 μm.
16 . The method of claim 1 , further comprising forming a bump on a side of the resin-based substrate that is opposite to a side of the RDL.
17 . The method of claim 16 , further comprising coupling the resin-based substrate to a printed circuit board (PCB) by the bump.
18 . The method of claim 1 , further comprising coupling the resin-based substrate to a printed circuit board (PCB) by a wire.
19 . The method of claim 1 , comprising forming an underfill between the IC and the resin-based substrate.
20 . The method of claim 1 , wherein the IC is configured to transfer heat directly to a heat sink.
21 . The method of claim 1 , further comprising forming at least one via to extend through the resin.
22 . The method of claim 1 , further comprising forming at least one via to extend through the IC.
23 . The method of claim 1 , further comprising forming an oxide layer prior to coupling the IC to the resin-based substrate.
24 . The method of claim 1 , further comprising performing chemical mechanical planarization (CMP) prior to coupling the IC to the resin-based substrate.
25 . The method of claim 1 , wherein forming the RDL comprises:
depositing the insulating layer on the resin-based substrate;
forming at least one hole in the insulating layer; and
depositing a metal layer on the insulating layer.
26 . The method of claim 1 , wherein coupling the IC to the resin-based substrate comprises at least one of:
a) forming a plurality of copper pillars on the RDL;
building the plurality of copper pillars on the IC;
performing face-to-face thermocompression bonding between the resin-based substrate and the IC; or
b) forming a plug on the IC and forming a plug on at least one MLCC of the plurality of MLCCs;
planarizing the resin-based substrate and the IC; and
performing face-to-face hybrid bonding between the resin-based substrate and the IC.
27 . A method for fabricating a module with reduced area, comprising:
forming a resin-based substrate;
forming a redistribution layer (RDL) on the resin-based substrate by:
depositing an insulating layer on the resin-based substrate;
forming at least one hole in the insulating layer; and
depositing a metal layer on the insulating layer; and
coupling an integrated circuit (IC) to the resin-based substrate.
28 . The method of claim 27 , wherein forming the resin-based substrate comprises:
attaching a plurality of multilayer ceramic capacitors (MLCCs) to a base sheet;
molding resin around the base sheet; and
performing one of: (a) removing the base sheet and adding the RDL at surfaces of the plurality of MLCCs from which the base sheet is removed; or (b) grinding the molded resin to surfaces of the plurality of MLCCs opposite to surfaces of the plurality of MLCCs facing the base sheet.
29 . The method of claim 27 , wherein coupling the IC to the resin-based substrate comprises at least one of:
a) forming a plurality of copper pillars on the RDL;
building the plurality of copper pillars on the IC;
performing face-to-face thermocompression bonding between the resin-based substrate and the IC; or
b) forming a plug on the IC and forming a plug on at least one MLCC of the plurality of MLCCs;
planarizing the resin-based substrate and the IC; and
performing face-to-face hybrid bonding between the resin-based substrate and the IC.
30 . A method for fabricating a module with reduced area, comprising one of:
a) forming a resin-based substrate by forming a resin on a plurality of multilayer ceramic capacitors (MLCCs);
forming a redistribution layer (RDL) in an insulating layer on the resin-based substrate; and
coupling an integrated circuit (IC) to the resin-based substrate by:
forming a plurality of copper pillars on the RDL;
building the plurality of copper pillars on the IC;
performing face-to-face thermocompression bonding between the resin-based substrate and the IC; or
b) forming a plug on the IC and forming a plug on at least one MLCC of the plurality of MLCCs;
planarizing the resin-based substrate and the IC; and
performing face-to-face hybrid bonding between the resin-based substrate and the IC.
31 . The method of claim 30 , wherein forming the resin-based substrate comprises:
attaching the plurality of multilayer ceramic capacitors (MLCCs) to a base sheet;
molding the resin around the base sheet; and
performing one of: (a) removing the base sheet and adding the RDL at surfaces of the plurality of MLCCs from which the base sheet is removed; or (b) grinding the molded resin to surfaces of the plurality of MLCCs opposite to surfaces of the plurality of MLCCs facing the base sheet.
32 . The method of claim 30 , wherein forming the RDL comprises:
depositing the insulating layer on the resin-based substrate;
forming at least one hole in the insulating layer; and
depositing a metal layer on the insulating layer.
33 . A package with reduced area, comprising:
a resin-based substrate comprising a plurality of multilayer ceramic capacitors (MLCCs) embedded in a resin;
a redistribution layer (RDL) in an insulating layer on the resin-based substrate;
an integrated circuit (IC) coupled to the resin-based substrate.